Abstract

This article outlines an optimal approach for board level CSP failure analysis, where the chip and printed circuit board are analyzed as a single unit to determine the root cause of the board level failures. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions, heating profiles or reflow, substrate warpage, and solder joint voids. This technique allows investigation of the above factors in a single sample preparation and readily arrive at the root cause solution in the minimum time. Results showed that package properties, the design of solder pads play the major role in determining how the fatigue behavior of solder joints will affect CSP component. Additional factors like nickel/gold and nickel palladium finishes were found to be more brittle and promote solder joint cracking.

This content is only available as a PDF.
You do not currently have access to this content.