Abstract

Silicon on Insulator (SOI) designed microprocessors offer first order benefits of lower power operation, reduced junction capacitance, and higher device densities; all combining in significant improvements in device performance and faster circuit level speeds [1,2,3,4]. Integrating SOI technology with lower resistance ( < 2 u Ω .cm )copper Back End of Line (BEOL) interconnections instead of aluminumcopper BEOL interconnection ( > 3 µ Ω -cm resistance ) offers further enhancements in microprocessor performance [5]. Electrical measurements of the sub 0.25ìm sized NFET and PFET devices contained in the embedded cells of these SOI designs pose new demands in developing alternative techniques and methods for both electrical characterization and physical analysis. MOSFET devices in IBM SOI designs do not tie the FET’s body to source but instead are allowed to “float” because of the insulating layer used in this technology [1,2,3,4] . Conventional methods of scanning electron microscopy, transmission electron microscopy, or focused ion beam microscopy where energetic ( >30kV) electron or ion beams are employed can produce unwanted effects affecting electrical and physical analysis. To minimize these effects, modifications in electrical characterization techniques as well as changes in FIB circuit analysis and sample preparation must be made to avoid the introduction of misleading electrical measurement results and artifacts in physical analysis results. Newer electrical characterization techniques such as atomic force microscopy imaging of submicron device features and physical AFM electrical probe contact measurements may be necessary when characterizing junction areas above the SOI insulating layer. Scanning capacitance microscopy is another technique successfully employed in pinpointing specific submicron device features in the embedded array cells. Specific sites less than 0.3ìm have been identified this way that correlate to anomalous electrically measured results. Subsequent transmission electron microscopy accuracy is further enhanced by this pinpointing technique. This successful localization permits enhanced TEM analysis involving electron energy loss spectroscopy (EELS) to detect the presence of low atomic number elements. The use of FIB to deposit chemical vapor deposited tungsten probe pads as an aid in assisting submicron device probing or circuit deletion/isolation of levels near the SOI insulating layer may induce unwanted charge build-up as well as introduce gallium ion leakage inimical to SOI designs. Similarly, changes in TEM sample preparation techniques must be adopted to avoid introducing induced artifacts and physical damages. In those instances where samples are thinned via FIB sectioning, the same concerns exist as described earlier (ie. introduction of unwanted charge buildup and/or gallium induced leakage paths). Specific features in CMOS latching circuits of SOI designs can now be pinpointed by using these modified electrical techniques, aided by the use of scanning capacitance microscopy and enhanced TEM physical analysis/sample preparation techniques.

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