Abstract
The repetitive energy discharge test (power cycling) is an accelerated stress test (AST) that can be used to characterize the long-term behavior of power transistors taking into account stress on customer final application. This paper describes the application of this test to an LDMOS transistor in order to optimize both design and size while preserving final reliability of the product. We will detail this reliability characterization program, emphasizing the power cycling tests performed in extreme conditions in order to reach and study physical limit of LDMOS devices. Analysis of LDMOS devices under these extreme conditions indicated evidence of metal voiding: the conditions of formation of these thermal fatigue induced voids will be discussed. The effect of major parameters like power cycling energy, ambient temperature will also be discussed. Electrical characterization of stressed devices will be presented. Finally, the results of the Transmission Electron Microscopy characterization of the metal microstructure will be discussed.