Continuous improvements over time to a CMOS Flash Memory technology resulted in significant improvement in Human Body Model (HBM) ESD immunity for “I/O’s” to Vcc power supply and Vss ground pins. Remaining low level failure modes in the die core included elevated standby current that in some cases could not be localized even with extensive chip de-processing. In addition an apparent functional failure upon post stress ATE test was isolated for certain part revisions. Routine separation of Vss/Vcc supply pin combinations from “all other pins” during HBM ESD test allowed identification of the several failures occurring in the die core. Failure analysis and corrective action is described. Additional diagnostic testing using separate polarity HBM pulses aided in tracing the conduction path causing the apparent functional failure and prompted investigation of HBM tester dynamic properties. It was determined that the magnitude of the “second” HBM pulse in certain testers was sufficient to cause a false powerup condition which results in apparent functional failure upon subsequent ATE test. In-situ monitoring of the Floating Power Bus response (in this case Vss) during application of HBM stress to the Input-pad to Vcc-pin combination revealed a transient caused by the “second” pulse that allowed such apparent failures to be invalidated. Further more, monitoring the in-situ floating Vss bus response to the HBM allowed conclusions to be drawn as to the utility of different power bus and Vss/Vcc supply clamp layouts, thereby allowing improvements to die layout to be implemented.

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