This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani  used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.