Abstract
Conventional reliability test using accelerated test is not suitable for selection of high-reliability LSI device, because it needs high cost and long testing time. Then observation methods such as construction analysis have been used in a part of the test. Construction analysis can detect faults on leads, packages wires and chip surfaces. However, recent LSI device structures have multilayers one, and most part of faults exist in inner layers. The faults are due to LSI wafer process imperfection such as inaccurate process design or device structural defects. LSI process diagnosis has been developed for the quality and reliability evaluation with the observation of device structures. It consists of fault detection and estimation of risk that the faults cause to fail more than one of devices through many manufacturing lots. Typically, cross sectional SEM for observation and data base or theory of reliability for risk estimation are used in this method.
