Abstract

Short-channel CMOS VLSI circuits can be presented in standby mode as a single effective MOSFET with inherent defects. This article proposes to apply failure analysis (FA) capabilities to a flow to define the product margin in a given process flavor. The experiments are performed on a microprocessor manufactured on a 0.25 pm CMOS process. The first part of this approach is to define the parametric baseline of the product, that is, to learn what is normal, and which parametric behavior is failure-prone. In the next section, different analytic and imaging techniques are applied for the inspection of the units which represent the baseline. The article presents the way to elucidate and measure the margin on each unit. The best way to do that is by means of the stress and this is discussed in the third section. The article also expands the knowledge obtained from FA for the characterization of product health.

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