This paper discusses the use of failure analysis techniques, including high-voltage stress testing, to determine the product margin for a microprocessor manufactured on a 0.25-μm CMOS process. The first part of the approach is to define the parametric baseline of the product and differentiate normal from failure-prone behavior. The next step is to measure the margin on each unit (i.e., transistor gate) by temporarily increasing the supply voltage (Vcc) and observing its effect on leakage current. As the authors explain, the new approach facilitates the detection of potential design and manufacturing problems in a much shorter time than the hundreds of hours normally required.

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