A novel backside-analysis technique has been developed to identify the locations of failing transistors in manufactured LSIs. Local gate doping depletion in p+ salicide gates of PMOSFETs, which reduces drain current, was visualized for the first time. Our method consists of backside etching and subsequent selective wet etching of the gate electrode. Si substrate material was removed with a highly selective Si etchant without damaging the gate-oxide film. After the gate-oxide film removal, a locally depleted gate was selectively etched using the same etchant. Since the etching rates of nondoped Si and n+ Si are much higher than that of p+ Si for the etchant, the depleted p+ gates were well defined. Through TEM observation, we found that a large grain lay on an active channel region of a PMOSFET. This led us to attribute the gate depletion to the difference in the impurity diffusion between large and small grains. This demonstration confirmed that our technique should be quite useful for identifying failing transistor locations in manufactured memory and logic LSIs.