Abstract

Logic fault diagnosis or fault isolation is the process of analyzing failing random logic portions of a chip to isolate the cause of failure. Fault diagnosis or fault isolation (FI) plays an important role in multiple applications at different stages of design and manufacturing. Most currently deployed FI techniques for random logic fault isolation include physical techniques with limited automated diagnosis followed by e-beam and/or laser voltage probing (LVP) on packaged parts. This paper will present the methodology and FI results obtained by executing automated scan based diagnosis on a chipset product (440BX). The logic diagnosis techniques used are presented along with simulation and Failure Analysis (FA) results

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