Abstract

This paper describes a method for applying passive voltage contrast (PVC) in the failure analysis of CMOS LSIs using a conventional scanning electron microscope (SEM), and demonstrates the effectiveness of this method. It was confirmed by measurement of the stage absorption current that the combined emission efficiency of secondary and backscattered electrons from aluminum is larger than 1 at acceleration voltages lower than about 2.5 kV. This means that local positive charges should be generated on a conductor in association with its irradiation with an electron beam at a relatively low acceleration voltage. However, a pn junction connected to the conductor would change the potential. The potential is still positive if the conductor is connected to a reverse-biased diode but becomes lower if such a diode is forward-biased. The PVC signal observed on the conductor should be defined according to the bias state of any diode connected to the conductor. Therefore, for failure analysis applications, if the bias state of a diode connected to a suspicious conductor is known, the PVC observation is useful for determining whether there is an open defect or a short-circuit defect. Some case studies are presented to demonstrate the effectiveness of the method. Cross-sectional TEM observations of defects localized in this way are also included.

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