Abstract

The ESD Association standard ANSI/ESDA S-5.1 1993 for testing sensitivity to the Human Body Model (HBM) 1 forms the basis around which the majority of automated HBM ESD simulators have been constructed. As device pin counts increase it is unlikely that new larger simulators for > 512 pins will be capable of meeting this standard 2, since increased parasitics will increase the effective socket (stray) capacitance. However, such larger HBM simulators are expected to meet both the JEDEC Standard JESD-22-114A, 1997 3 and the newly issued ESDA Standard Test Method, ESD STM 5.1, 19984. This paper begins to evaluate the several questions regarding the correlation of HBM Withstand Voltage when used to characterize state-of-the-art semiconductor IC's, between simulators meeting the (NEW) standards JESD 22, ESD STM- 5.1 and those existing simulators presently in daily use, which typically meet the (OLD) ESDA S-5.1. This paper for the first time investigates the impact of “effective” socket capacitance in the same tester; i.e., with the same discharge model and the same pin selection mechanism. The experimental investigation was based on stressing three different sub-micron CMOS technology products; firstly on a simulator meeting the OLD standard and then on a modified version of this simulator meeting the NEW standards. Electrical properties of damaged pins and physical analysis was used to establish common Failure Signatures5 for the two mother boards.

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