Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

dislocations, failure anlysis, memory devices, static random access memory, transmission electron microscopy, wafer level testing
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Copyright © 1998 ASM International. All rights reserved.
1998
ASM International
Topics
Transmission electron microscopy Semiconductor wafer fabrication
Issue Section:
Techniques
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