Abstract

New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

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