Innovative Application of a Passive Device Failure Analysis Technique to a JFET

A technique normally used for the analysis of tantalum capacitor failures was successfully applied to a JFET. The JFET had a short from the source to the gate. The short was located at the source bond pad and had resulted from a combination of the use of too large a bond wire and excessive bonding pressure. The exact location of the site of the short was successfully determined by using a copper electroplating technique typically used for locating shorts or leakage sites on the tantalum slug of a tantalum capacitor.