The Logic Mapper software created by Knights Technology bridges the gap between traditional yield enhancement techniques in the wafer fab and analytical failure techniques in the failure analysis (FA) laboratory. With Logic Mapper, fabs can test logic devices as easily as memory devices. Traditional logic chip yield enhancement techniques within product engineering and wafer fab yield enhancement organizations rely heavily on binsort functional test correlation to anticipate and correct semiconductor process issues. Some of the key shortcomings of these techniques are: · The inability to relate a particular bin’s fallout to a suspect process level. · The inability to distinguish a defect-driven yield issue from a device-integration issue. · The inability to establish a clear link between large populations of failed die. Logic Mapper resolves these key shortcomings by taking the output from functional testers and translating it from a list of failed scan chains into a list of suspected netlist nodes. Using Merlin’s FrameworkTM software, the netlist can be used to identify the X, Y coordinates of a suspected failing node; the failure analysis and yield enhancement engineers have created a starting point for investigating failures. These nodes can then be crossmapped from the circuit design onto the chip’s layout over multiple photomask layers within the design. The ability to translate a logic device’s binsort functional test fail data to defect traces is an advancement in the quality of test information provided for failure analysis and yield enhancement.

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