An investigation into a high resistance via problem during the development phase of an advanced 0.25µm CMOS ASIC process is presented. The electrical signature of the via problem was low yield on filly processed device wafers. Further testing revealed that the logic (cell-based) sections of the chip were fimctioning, however the 512K bit SRAM was consistently failing. Based on the failing bit pattern, the failure area was isolated to contacthia stacks in the cell. Advanced wafer level failure analysis techniques and equipment such as focus-ionbeam milling, precision cross-section, and pkmar polishing techniques were utilized to identifi the layer that was failing. Analysis results indicated a thin foreign layer or void between the aluminum line and the cap barrier layer of the line. Placement of a via on this line resulted in a high resistance node and subsequent device failure. As a further verification of the electrical failing signature, SPICE simulation was run on the SRAM cell circuitry. Optimization of the metallization stack was performed through experiments which resulted in the elimination of the mechanism.