Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. To deal with the challenge of faster and more accurate defect localization with greater sensitivity, we have developed a new method based on voltage contrast capabilities for internal localization of IDDQ defects. This method covers an extended range of cases: functional or non functional devices, with or without CAD information, etc... Using only the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located. This approach can also be extended to coupling with netlist information. For example, the equipotential line previously found on the faulty circuit can be compared with the fault simulator output. Then, the site of the simulated defect corresponding to the physical failure can be extracted and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.