Abstract

A selected area planar TEM (SAPTEM) sample preparation technique for failure analysis of integrated circuits using a transmission electron microscope has been developed. The technique employs a combination of mechanical grinding, selective wet/dry chemical etching (if required) and a two step focused ion beam IIFIB) milling. The mechanical grinding steps include: (a) a backside grind to achieve a die thickness less than 30 µm, (b) the support half ring glue, and (c) a cross-section grind from one side to reach less than 35 pm to the failing site. A selective wet or dry chemical etch is applied before, between,, or after FIB thinning depending on the nature of problem and device components. The FIB milling steps involve: (is) a high ion current cross-sectional cut to reach as close as 5-8 µm to the area of interest (b) a final planar thinning with the ion beam parallel to the surface of the die. The plan view procedure offers unique geometric advantage over the cross-section method for failure analysis of problems that are limited to silicon or certain layers of the device. Iln the cross-sectional approach, a thin section (thickness less than 250 µm) of a device is available for failure analysis, whereas in the planar procedure a 20 µm2 area of any layer (thickness less than 250 µm) of the device is available. The above advantage has been successfully exploited to identify and solve the following prablems in fast static random access memories (FSRAM): (i) random gateoxide rupture that resulted in single bit failures, (ii) random dislocations from the buried contact trenching that caused single bit failures and general silicon defectivity (e.g. implant damage and spacer edge defects), and (iii) interracial reactions.

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