In IDDQ testing of CMOS ASICs (as in conventional voltage based testing) actual defect coverage, rather than modeled fault coverage figures are relevant to achieving product Q&R targets. This paper reports experimental data on the defect coverage of IDDQ vectors taken from several ASICs from different semiconductor suppliers. We present our generic IDDQ methodology that has been run on these ASICs, including automated IDDQ vector generation/grading and the high speed IDDQ monitor OCIMU. Data are presented on absolute IDDO defect coverage, as estimated from correlation with voltage based tests, on the relative defect coverage of pseudo-stuck-at and the toggle fault models, on the defect coverage of reduced IDDQ sets and on the pattern sensitivity Of IDDQ rejects. It is demonstrated that the pictures shown by modeled fault coverage and actual defect coverage can differ significantly and therefore, theoretical fault coverage figures are not the correct data to assure Q&R targets. We have measured very good IDDQ defect coverage on random logic, but we also show real life cases where IDDQ testing alone is inefficient in screening Q&R hazards.