The feasibility of the vision of the Semiconductor Industry Association (SIA) Road Maps is rooted in a number of important assumptions. One of them is a requirement of up to 90% yields, which must be achieved for each of the subsequent SIA Road Map milestones. This article argues that such high yields cannot be achieved without a substantial increase in the efficiency of failure analysis. Consequently, it is indicated that testing-based failure analysis is the only alternative which must eventually take over the major responsibility for yield ramping. Finally, it is demonstrated that the increase in the cost of manufacturing due to the increase in failure analysis cost can be justified by extra revenue obtained via faster yield ramping. The article suggests that the testing and IC Design for Diagnosability-based rapid failure analysis are key elements for successful realization of the SIA Road Map objectives.