In the last several years emission microscopy has become an essential tool for failure analysis, specifically for VLSI devices. This paper describes various die related failure mechanisms in CMOS ASIC devices which were detected by emission microscopy. The failure analysis results discussed in this paper are primarily of the devices which were analyzed over the period of the last three years, 1994 - 1996. These devices were from a broad spectrum of final test failures, qualification and reliability test failures, special evaluation failures, testing and assembly failures at customer sites, and end user field failures. In addition to the failure mechanism statistic scanning electron micrographic illustrations of some of the failure mechanisms and associated damage are presented in this paper. The data presented in this paper clearly show the effectiveness of photon emission microscopy. The value of emission microscopy really lies in quick detection of failure locations on the die which failed functionally or due to excessive static IOD, functional IOD, or input/output leakage currents. It has certainly impacted tum around time of the analysis as significant reduction in analysis time has been achieved. In some cases same day turn around was possible.

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