A Process Induced Failure Mechanism in the EEPROM Cell - Its Identification and Solution

A 0.8 μm technology based Electrical Erasable, Programmable Read-Only Memory (EEPROM) cell having a high voltage select transistor and a floating gate transistor with a control gate on top as used in the Motorola Neuron product chip set was analyzed for program and erase failure. Silicon pitting in the select transistor channel was identified to be the failure mechanism. The silicon pitting was experimentally confirmed to be attributed to the penetration of the bottom oxide in the oxide-nitride-oxide (ONO) structure due to the nitride removal using reactive ion etching (RIE). A modified process flow with a thicker sacrificial oxide under the nitride eliminated the pitting failure mechanism and enhanced yield and reliability.