The increasing popularity of flip-chips brings new challenges to those who must perform device analysis (1). Its ability to accommodate high pin-count and high bandwidth microprocessors, DSPs and complex logic devices is increasing the demand for this technology. Conventional e-beam and mechanical probing techniques currently allow quick and efficient analysis of conventional semiconductor devices. When the surface of the device is not exposed, however, conventional analysis techniques are insufficient and new techniques must be developed. Conventional packaging technologies allow design debug and failure analysis to be performed in a relatively straightforward manner. Analysis from the topside is clearly the preferred technique when possible (2), using specially prepared engineering prototypes, but backside access for dynamic timing analysis is required when topside techniques are exhausted. The flipchip process, however, makes topside analysis impractical in most situations. There are several different techniques that are currently being used for backside analysis. These are emission microscopy (3), optical beam induced current (OBIC) (4), and a combination of software and built in self-test/scan methods (5). These techniques are valuable in helping engineers to analyze and isolate faults for functional failures. These techniques do not, however, provide precise analog waveforms which may be used to perform timing analysis on the device. A backside pulsed laser electro-optic technique for measuring internal node timing (6) has been developed for waveform acquisition. Although this technique permits acquisition of waveforms from a bi-polar device which has had its substrate thinned, it has limited application to CMOS devices, particularly in long duty cycle applications. Milling the backside of devices in order to facilitate backside waveform acquisition is considered by some researchers as a potential approach, but the authors are not aware of any published data on this subject.

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