A strategy for improving yield lately is this: wafers are electrically tested to determine which chips are defective. Defects are located and classified by the failure analyst who establishes a root cause for each type of defect. This information is delivered to the process engineers who then eliminate the root causes of the most frequently occurring defects. This process is known as TPLY. for Tested Product Limited Yield. This method gives the physical failure analyst the job of finding statistical numbers of defects. Defects are located by deprocessing chips and examining them with an optical or electron microscope, usually in an area of the chip identified by a bit fail map or some other technique, such as liquid crystal hot spot detection. This presentation offers practical suggestions for improving the efficiency of the TPLY process. It includes general considerations for TPLY, methods for delayering chips and finding defects quickly, and statistical methods for identifying the cause of low yield with minimum sample sizes. A simple yield model is developed for relating test site yield to product chip final test yield, and explains why test sites do not always adequately predict yield of the product. Case studies and other examples are discussed to demonstrate the application of these techniques.

This content is only available as a PDF.
You do not currently have access to this content.