The paper describes the approach that was developed to cope with the specific difficulties encountered with FIB circuit modification on the 0.5 and 0.35um technologies from a multitude of silicon vendors. This approach involves adaptations in FIB hardware (insulator deposition), software (image alignment), design practice (alignment marks, spare parts, routing recommendations) and FIB practice (procedure for node localisation and contacting, via drill and fill). The latter seems to be a major factor limiting FIB circuit repair feasibility: although it is perfectly feasible to drill deep and small vias (e.g. between minimum spacing overlying metallization), it is not evident to reproducibly fill such holes and obtain a good and reliable via resistance. This limits the minimum size of FIB vias to deep circuit nodes. The developed total approach enables to continue the use of FIB for circuit repair on the new generations of processes, with all the well-known benefits w.r.t. cost savings and Time-To-Market.