As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.