A new logic-model derivation method for leak faults observed by light-emission microscopy (LEM) or in liquid-crystal analysis (LCA) has been developed to verify those faults by comparing them with failures observed on an LSI tester. Since CMOS devices display various kinds of faulty behavior depending on leak resistance, it is essential to include the effects of this resistance in logic models. Considering that the resistance of leaks observed in LEM and LCA ranges from 10 to 10,000 ohm, the new logic models have been derived so that the leak fault could be easily incorporated into logic simulators without SPICE simulation. The feasibility of the proposed method has been demonstrated by using it to diagnose LEM and LCA faults causing logic failure in a 20k-gate logic LSI circuit.

CMOS devices, electronic circuits, failure analysis, fault verification simulation, large scale integration, leak resistance, light emission microscopy, liquid crystal analysis, logic simulators, logic-model derivation methods
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Copyright © 1996 ASM International. All rights reserved.
1996
ASM International
Topics
Photoemission electron microscopy Semiconductor wafer fabrication
Issue Section:
Software Tools for Failure Analysis
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