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ISTFA 2003

November 2–6, 2003

Santa Clara, California, USA

Conference Sponsors:

Electronic Device Failure Analysis Society
ASM International

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis

Issue navigation

Advanced Techniques
Optical Techniques
Package Level Analysis
Sample Preparation
System Level Analysis
Metrology and Materials Analysis
Failure Analysis Process
Metrology and Materials Analysis
Test
Poster Session
Circuit Edit
Die Level Fault Isolation
Scanning Probe Microscopy
Optoelectronic Devices
Discretes
Sample Preparation
Yield Enhancement
Test
Volume Information

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis

Advanced Techniques

Scanning Magnetoresistive Microscopy for Die-Level Sub-Micron Current Density Mapping

B. D. Schrag; X. Y. Liu; M. J. Carter; Gang Xiao

ISTFA 2003; 2-5https://doi.org/10.31399/asm.cp.istfa2003p0002

View Articletitled, Scanning Magnetoresistive Microscopy for Die-Level Sub-Micron Current Density Mapping

High Resolution Current Imaging by Direct Magnetic Field Sensing

S.I. Woods; Nesco M. Lettsome, Jr.; A.B. Cawthorne; L.A. Knauss; R.H. Koch

ISTFA 2003; 6-8https://doi.org/10.31399/asm.cp.istfa2003p0006

View Articletitled, High Resolution Current Imaging by Direct Magnetic Field Sensing

Fault Isolation of High Resistance Defects Using Comparative Magnetic Field Imaging

Antonio Orozco; Elena Talanova; Anders Gilbertson; L.A. Knauss; Zhiyong Wang; Lars Skoglund; David G. Smith; Rajen Dias

ISTFA 2003; 9-13https://doi.org/10.31399/asm.cp.istfa2003p0009

View Articletitled, Fault Isolation of High Resistance Defects Using Comparative Magnetic Field Imaging

High Resolution Backside Thermography Using a Numerical Aperture Increasing Lens

S. Thorne; S. Ippolito; M. Eraslan; B. Goldberg; M.S. Ünlü; Y. Leblebici

ISTFA 2003; 14-17https://doi.org/10.31399/asm.cp.istfa2003p0014

View Articletitled, High Resolution Backside Thermography Using a Numerical Aperture Increasing Lens

Optical Techniques

Study of Critical Factors Determining Latchup Sensitivity of ICs Using Emission Microscopy

Franco Stellari; Peilin Song; Moyra K. McManus; Alan J. Weger; Robert J. Gauthier; Kiran V. Chatty; Mujahid Muhammad; Pia Sanda

ISTFA 2003; 19-24https://doi.org/10.31399/asm.cp.istfa2003p0019

View Articletitled, Study of Critical Factors Determining Latchup Sensitivity of ICs Using Emission Microscopy

New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM)

R. Aaron Falk; Neil Bauersfeld; Mark LaPierre; Shawn Elliott

ISTFA 2003; 25-35https://doi.org/10.31399/asm.cp.istfa2003p0025

View Articletitled, New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM)

PC Card Based Optical Probing of Advanced Graphics Processor Using Time Resolved Emission

Howard Lee Marks; Tung Ton; Jeffrey A. Block; Steven Kasapi; Chris Shaw

ISTFA 2003; 36-39https://doi.org/10.31399/asm.cp.istfa2003p0036

View Articletitled, PC Card Based Optical Probing of Advanced Graphics Processor Using Time Resolved Emission

Time-Resolved Optical Measurements from 0.13μm CMOS Technology Microprocessor Using a Superconducting Single-Photon Detector

Franco Stellari; Peilin Song; Alan J. Weger; Moyra K. McManus

ISTFA 2003; 40-44https://doi.org/10.31399/asm.cp.istfa2003p0040

View Articletitled, Time-Resolved Optical Measurements from 0.13μm CMOS Technology Microprocessor Using a Superconducting Single-Photon Detector

IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling

Romain Desplats; Alban Eral; Felix Beaudoin; Philippe Perdu; Alain Chion; Ketan Shah; Ted Lundquist

ISTFA 2003; 45-54https://doi.org/10.31399/asm.cp.istfa2003p0045

View Articletitled, IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling

Package Level Analysis

3D X-ray Computed Tomography (CT) for Electronic Packages

Zezhong Fu; Deepak Goyal; Jeffrey Thomas; Alan Crawley; Andrew Ramsey

ISTFA 2003; 56-61https://doi.org/10.31399/asm.cp.istfa2003p0056

View Articletitled, 3D X-ray Computed Tomography (CT) for Electronic Packages

High-Angle Electron Microscopy Technique for Analysis of Thin Film Contamination on IC Package Exteriors

Thomas Barbieri; Jake Schaper; Pete Dimuzio

ISTFA 2003; 62-67https://doi.org/10.31399/asm.cp.istfa2003p0062

View Articletitled, High-Angle Electron Microscopy Technique for Analysis of Thin Film Contamination on IC Package Exteriors

Solder Bump Defects in Ceramic Flip Chip Packages and Their Acoustic Signatures

Kartik Ramanujachar; Darwin Rusli; Reena Agarwal; James Widaski

ISTFA 2003; 68-75https://doi.org/10.31399/asm.cp.istfa2003p0068

View Articletitled, Solder Bump Defects in Ceramic Flip Chip Packages and Their Acoustic Signatures

Copper Bond Over Active Circuit (BOAC) and Copper Over Anything (COA) Failure Analysis

Dat Nguyen; Bob Davis; Corey Lewis

ISTFA 2003; 76-81https://doi.org/10.31399/asm.cp.istfa2003p0076

View Articletitled, Copper Bond Over Active Circuit (BOAC) and Copper Over Anything (COA) Failure Analysis

Investigation of Bond-Pad Related Inter-Metal Dielectric Crack

Z. G. Song; T. Tun; C. K. Oh; S. Redkar; B.H. Er; C. P. Soo; C. H. Goo

ISTFA 2003; 82-85https://doi.org/10.31399/asm.cp.istfa2003p0082

View Articletitled, Investigation of Bond-Pad Related Inter-Metal Dielectric Crack

Sample Preparation

Enhanced SEM Doping Contrast

C.Y. Lin; J. H. Lee

ISTFA 2003; 87-89https://doi.org/10.31399/asm.cp.istfa2003p0087

View Articletitled, Enhanced SEM Doping Contrast

Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis

Huixian Wu; James Cargo; Barry Dutt; Tony Bucha; Joe Serpiello

ISTFA 2003; 90-98https://doi.org/10.31399/asm.cp.istfa2003p0090

View Articletitled, Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

Seth J. Prejean; Joseph Shannon

ISTFA 2003; 99-104https://doi.org/10.31399/asm.cp.istfa2003p0099

View Articletitled, Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

A Novel Approach to Front-Side Deprocessing for Thinned Die after Backside Failure Isolation

Dat Nguyen; Cuong Phan; Jeff Conner; Martin Smith; John Drummond

ISTFA 2003; 105-109https://doi.org/10.31399/asm.cp.istfa2003p0105

View Articletitled, A Novel Approach to Front-Side Deprocessing for Thinned Die after Backside Failure Isolation

Backside Imaging and AFM Profiling of Tunnel Oxide, Poly 1, ONO and Poly 2 Layers on Flash Devices

Kaushal Upadhyaya; Patrice W. Blacker

ISTFA 2003; 447-451https://doi.org/10.31399/asm.cp.istfa2003p0447

View Articletitled, Backside Imaging and AFM Profiling of Tunnel Oxide, Poly 1, ONO and Poly 2 Layers on Flash Devices

Sample Preparation Techniques for Analysis and Debug of Circuits with Cu Inductors and Thick Organic Dielectric

Mauri Sutton; Scott Kiefer; Syd Wilson; Manoj Nair; Paul Sanders; John Steele; Wayne Paulson

ISTFA 2003; 452-455https://doi.org/10.31399/asm.cp.istfa2003p0452

View Articletitled, Sample Preparation Techniques for Analysis and Debug of Circuits with Cu Inductors and Thick Organic Dielectric

Laser Interferometer Specimen Preparation of PCB Assembled Components at Second Level Interconnect for In-plane Shear Strain Measurements

William J. Cunningham

ISTFA 2003; 456-464https://doi.org/10.31399/asm.cp.istfa2003p0456

View Articletitled, Laser Interferometer Specimen Preparation of PCB Assembled Components at Second Level Interconnect for In-plane Shear Strain Measurements

A Novel Fault Isolation Technique for Identifying Deep Sub-Micron Defects

Fayik M. Bundhoo; Soundaranathan Kasivisvanatha

ISTFA 2003; 465-469https://doi.org/10.31399/asm.cp.istfa2003p0465

View Articletitled, A Novel Fault Isolation Technique for Identifying Deep Sub-Micron Defects

System Level Analysis

Dynamic Infrared System Level Fault Isolation

John A. Naoum; Johan Rahardjo; Yitages Taffese; Marie Chagny; Jeff Birdsley; John C. Woo; Aaron Morris

ISTFA 2003; 111-119https://doi.org/10.31399/asm.cp.istfa2003p0111

View Articletitled, Dynamic Infrared System Level Fault Isolation

X-ray Laminography Benchmarking and Failure Analysis of Solder Joint Interfaces

Barbara A. Thomson; Norman J. Armendariz

ISTFA 2003; 120-124https://doi.org/10.31399/asm.cp.istfa2003p0120

View Articletitled, X-ray Laminography Benchmarking and Failure Analysis of Solder Joint Interfaces

XRF Correlation of Board Reseats Due to Intermittent Failures from the Use of Thin Gold Plating finish on the Contact Fingers

Dan Stein; Victor Hernandez; Mary Ann Nailos

ISTFA 2003; 125-130https://doi.org/10.31399/asm.cp.istfa2003p0125

View Articletitled, XRF Correlation of Board Reseats Due to Intermittent Failures from the Use of Thin Gold Plating finish on the Contact Fingers

Metrology and Materials Analysis

Real Time SEM Imaging of FIB Milling Processes for Extended Accuracy on TEM Samples for EFTEM Analysis

P. Gnauck; U. Zeile; P. Hoffrogge; G. Benner; A. Orchowski; W-D. Rau

ISTFA 2003; 132-139https://doi.org/10.31399/asm.cp.istfa2003p0132

View Articletitled, Real Time SEM Imaging of FIB Milling Processes for Extended Accuracy on TEM Samples for EFTEM Analysis

A Method for Exact Determination of DRAM Deep Trench Surface Area

Jeremy D. Russell; Yuan-Wei Tseng

ISTFA 2003; 140-143https://doi.org/10.31399/asm.cp.istfa2003p0140

View Articletitled, A Method for Exact Determination of DRAM Deep Trench Surface Area

A Review of TEM Observations of Failures of the Memory Cell in a Deep Trench Capacitor DRAM

Jen-Lang Lue; Jack Lee; Esther Chen; Jian-Shing Luo

ISTFA 2003; 144-152https://doi.org/10.31399/asm.cp.istfa2003p0144

View Articletitled, A Review of TEM Observations of Failures of the Memory Cell in a Deep Trench Capacitor DRAM

The Effect of TEM Specimen Preparation Method on Ultra-Thin Gate Dielectric Analysis

A. Y. Du; C. H. Tung; B. H. Freitag; W. Y. Zhang; S. Lim; E. H. Ang; Danny Ng

ISTFA 2003; 153-157https://doi.org/10.31399/asm.cp.istfa2003p0153

View Articletitled, The Effect of TEM Specimen Preparation Method on Ultra-Thin Gate Dielectric Analysis

Forward Scattered Scanning Electron Microscopy for Semiconductor Metrology and Failure Analysis

William E. Vanderlinde

ISTFA 2003; 158-165https://doi.org/10.31399/asm.cp.istfa2003p0158

View Articletitled, Forward Scattered Scanning Electron Microscopy for Semiconductor Metrology and Failure Analysis

Contact Failure Due to Particulate Defect in a 0.13 µm CMOS Process

Sandeep Bagchi; Valli Arunachalam; Javier Saenz; James Beck; Lupe Duncan; Jim Conner

ISTFA 2003; 206-208https://doi.org/10.31399/asm.cp.istfa2003p0206

View Articletitled, Contact Failure Due to Particulate Defect in a 0.13 µm CMOS Process

Microhardness Testing on Via Fill Material for Via In Pad Technology

Norman J. Armendariz; Carolyn McCormick

ISTFA 2003; 209-214https://doi.org/10.31399/asm.cp.istfa2003p0209

View Articletitled, Microhardness Testing on Via Fill Material for Via In Pad Technology

Application of ToF-SIMS to Airborne Organic Contamination Analysis

Dong Lu; Alastair Trigg; Zhenxiang Xing; Rakesh Kumar; Chang Kuo Chang

ISTFA 2003; 215-220https://doi.org/10.31399/asm.cp.istfa2003p0215

View Articletitled, Application of ToF-SIMS to Airborne Organic Contamination Analysis

Failure Analysis Process

Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results

Steve Ferrier; Kevin D. Martin; Donald Schulte

ISTFA 2003; 167-176https://doi.org/10.31399/asm.cp.istfa2003p0167

View Articletitled, Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results

SRAM Failure Analysis Strategy

P. Egger; C. Burmer

ISTFA 2003; 177-183https://doi.org/10.31399/asm.cp.istfa2003p0177

View Articletitled, SRAM Failure Analysis Strategy

VLSI Design for Functional Failure Analysis in the < 90 nm and Flip-Chip Era

Yoav Weizman; Ezra Baruch

ISTFA 2003; 184-190https://doi.org/10.31399/asm.cp.istfa2003p0184

View Articletitled, VLSI Design for Functional Failure Analysis in the < 90 nm and Flip-Chip Era

Identification of an I_DDQ Failure Mechanism Using a Variety of Front and Backside Analytical Techniques

Jim Shearer; Kim Le; Xiaoyu Yang; Monty Cleeves; Al Meeks

ISTFA 2003; 191-196https://doi.org/10.31399/asm.cp.istfa2003p0191

View Articletitled, Identification of an <em>I<sub>DDQ</sub></em> Failure Mechanism Using a Variety of Front and Backside Analytical Techniques

Novel Application of Transmission Electron Microscopy and Scanning Capacitance Microscopy for Defect Root Cause Identification and Yield Enhancement

P. Tangyunyong; T. A. Hill; C. Y. Nakakura; J. M. Soden; E. I. Cole, Jr.; R. S. Flores; M. R. Shaneyfelt; R. C. Dockerty; T. J. Headley; M. J. Rye

ISTFA 2003; 197-204https://doi.org/10.31399/asm.cp.istfa2003p0197

View Articletitled, Novel Application of Transmission Electron Microscopy and Scanning Capacitance Microscopy for Defect Root Cause Identification and Yield Enhancement

Test

Yield-Modeling and Test Oriented Taxonomy of IC Structure Deformations

W. Maly; T. Zanon; T. Vogels

ISTFA 2003; 222-231https://doi.org/10.31399/asm.cp.istfa2003p0222

View Articletitled, Yield-Modeling and Test Oriented Taxonomy of IC Structure Deformations

Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps

T. Zanon; M. Ferdman; W. Maly; K. Komeyli

ISTFA 2003; 232-241https://doi.org/10.31399/asm.cp.istfa2003p0232

View Articletitled, Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps

Electrical Failure Analysis and Characterization of Leakage Paths Leading to Single Cell Failures in 128Mbit SDRAMs

M. Versen; A. Schramm

ISTFA 2003; 242-247https://doi.org/10.31399/asm.cp.istfa2003p0242

View Articletitled, Electrical Failure Analysis and Characterization of Leakage Paths Leading to Single Cell Failures in 128Mbit SDRAMs

Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel In-Situ Methodology

C.D. Hartfield; J.J. Broz; T.M. Moore

ISTFA 2003; 486-495https://doi.org/10.31399/asm.cp.istfa2003p0486

View Articletitled, Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel <em>In-Situ</em> Methodology

A Multi-Stage Approach to Fault Identification Using Fault Tuples

R. Desineni; T. J. Vogels; K. N. Dwarakanath; T. Zanon; R. D. Blanton; W. Maly

ISTFA 2003; 496-505https://doi.org/10.31399/asm.cp.istfa2003p0496

View Articletitled, A Multi-Stage Approach to Fault Identification Using Fault Tuples

Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment

Eric Liau; Doris Schmitt-Landsiedel

ISTFA 2003; 506-513https://doi.org/10.31399/asm.cp.istfa2003p0506

View Articletitled, Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment

Poster Session

A Study on Fluorine-Induced Corrosion on Microchip Aluminum Bondpads

Y. N. Hua; S. Redkar; Ron Dickinson; S. L. Peh; Shirley

ISTFA 2003; 249-255https://doi.org/10.31399/asm.cp.istfa2003p0249

View Articletitled, A Study on Fluorine-Induced Corrosion on Microchip Aluminum Bondpads

Advanced Process Defect Detection by Using Dynamic Bias Condition and MCT Camera

Ching-Wei Wu; Jeng-Han Lee

ISTFA 2003; 256-258https://doi.org/10.31399/asm.cp.istfa2003p0256

View Articletitled, Advanced Process Defect Detection by Using Dynamic Bias Condition and MCT Camera

Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques

Srikanth Perungulam; Albert Gleason

ISTFA 2003; 259-261https://doi.org/10.31399/asm.cp.istfa2003p0259

View Articletitled, Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques

ESD Failure Signature Differences in the Devices Core Logic and Protection Structures - A Case Study

Leo G. Henry

ISTFA 2003; 262-271https://doi.org/10.31399/asm.cp.istfa2003p0262

View Articletitled, ESD Failure Signature Differences in the Devices Core Logic and Protection Structures - A Case Study

ESD: Correlation between Electrical Signature and Failure Modes

V. Korchnoy; B. Lisenker; I. Posimeinik

ISTFA 2003; 272-277https://doi.org/10.31399/asm.cp.istfa2003p0272

View Articletitled, ESD: Correlation between Electrical Signature and Failure Modes

Semi-Automated Cross-Section Preparation Process for Complex Multi-Face Perimeter Samples

Todd McDonald

ISTFA 2003; 278-281https://doi.org/10.31399/asm.cp.istfa2003p0278

View Articletitled, Semi-Automated Cross-Section Preparation Process for Complex Multi-Face Perimeter Samples

FIB Micro-Pillar Sampling of Si Devices and its 3D Observation

T. Yaguchi; T. Kamino; T. Ohnishi; T. Hashimoto; K. Umemura; K. Asayama

ISTFA 2003; 282-287https://doi.org/10.31399/asm.cp.istfa2003p0282

View Articletitled, FIB Micro-Pillar Sampling of Si Devices and its 3D Observation

Recent Developments in Automated Sample Preparation for FESEM

R. R. Cerchiara; P. E. Fischione; J. J. Gronksy; W. F. Hein; D. D. Martin; J. M. Matesa; A. C. Robins; D. W. Smith

ISTFA 2003; 288-296https://doi.org/10.31399/asm.cp.istfa2003p0288

View Articletitled, Recent Developments in Automated Sample Preparation for FESEM

Wet Delineation of SEM Samples Having Cu Interconnects

J.B. Lai; Y.P. Wang; J.Y. Kung; Y.C. Fu; R.L. Hwang; David Su

ISTFA 2003; 297-300https://doi.org/10.31399/asm.cp.istfa2003p0297

View Articletitled, Wet Delineation of SEM Samples Having Cu Interconnects

An Evolution in Plastic Decapsulation Process Improvement

N.S. Somcio; Andrew J. Komrowski; Luis Curiel; Charles R. Silvis; Daniel J.D. Sullivan

ISTFA 2003; 301-304https://doi.org/10.31399/asm.cp.istfa2003p0301

View Articletitled, An Evolution in Plastic Decapsulation Process Improvement

Obtaining Low Contact Resistance for Physical Sub-Micron Fault Isolation

C. A. Waggoner; D. Smith

ISTFA 2003; 305-310https://doi.org/10.31399/asm.cp.istfa2003p0305

View Articletitled, Obtaining Low Contact Resistance for Physical Sub-Micron Fault Isolation

Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Devices

W.B. Len; Y.Y. Liu; J.C.H. Phang; D.S.H. Chan

ISTFA 2003; 311-316https://doi.org/10.31399/asm.cp.istfa2003p0311

View Articletitled, Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Devices

Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment

Yuan-Shih Chen; Jeng-Han Lee

ISTFA 2003; 317-319https://doi.org/10.31399/asm.cp.istfa2003p0317

View Articletitled, Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment

A Flexible, Low Cost Test System for Failure Analysis of High Power Mixed Signal ASICs

T. Kolasa; J. C. De La Torre; L. Bertram

ISTFA 2003; 320-324https://doi.org/10.31399/asm.cp.istfa2003p0320

View Articletitled, A Flexible, Low Cost Test System for Failure Analysis of High Power Mixed Signal ASICs

Photoemission and OBIRCH Analysis with Solid Immersion Lens (SIL)

Ikuo Arata; Shigeru Sakamoto; Yoshiyuki Yokoyama; Hirotoshi Terada

ISTFA 2003; 325-329https://doi.org/10.31399/asm.cp.istfa2003p0325

View Articletitled, Photoemission and OBIRCH Analysis with Solid Immersion Lens (SIL)

Circuit Edit

Voltage Contrast like Imaging of N-Wells

Christian Boit; Kristin R. Wirth; Erwan Le Roy

ISTFA 2003; 331-337https://doi.org/10.31399/asm.cp.istfa2003p0331

View Articletitled, Voltage Contrast like Imaging of N-Wells

Improvements of Secondary Electron Imaging and Endpoint Detection in Focused Ion Beam Circuit Modification

Valery Ray; Nicholas Antoniou; Alex Krechmer; Andrew Saxonis

ISTFA 2003; 338-342https://doi.org/10.31399/asm.cp.istfa2003p0338

View Articletitled, Improvements of Secondary Electron Imaging and Endpoint Detection in Focused Ion Beam Circuit Modification

Modeling Secondary Electron Emission from High Aspect Ratio Holes

Q. S. Wang; M. A. Thompson; W. Schultz; T. R. Lundquist

ISTFA 2003; 343-347https://doi.org/10.31399/asm.cp.istfa2003p0343

View Articletitled, Modeling Secondary Electron Emission from High Aspect Ratio Holes

The Impact of Feature Packing Density on FIB Editing of Advanced Technology ICs

H. Marchman; S. Herschbein; C. Scrudato; C. Rue; L. Fischer; M. Abramo

ISTFA 2003; 348-354https://doi.org/10.31399/asm.cp.istfa2003p0348

View Articletitled, The Impact of Feature Packing Density on FIB Editing of Advanced Technology ICs

Small Via High Aspect Ratio Circuit Edit: Challenges, Techniques and Developments

Valery Ray; Nicholas Antoniou; Ravi Balasubramanian; Neil Bassom; Marie Clabby; Tom Gannon; Chuong Huynh; Gary Tiani

ISTFA 2003; 355-361https://doi.org/10.31399/asm.cp.istfa2003p0355

View Articletitled, Small Via High Aspect Ratio Circuit Edit: Challenges, Techniques and Developments

Die Level Fault Isolation

Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling

Randal Mulder; Sam Subramanian; Ed Widener; Tony Chrastecky

ISTFA 2003; 363-370https://doi.org/10.31399/asm.cp.istfa2003p0363

View Articletitled, Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling

Laser Stimulation Applied to Dynamic IC Diagnostics

Félix Beaudoin; Romain Desplats; Philippe Perdu; Abdellatif Firiti; Gerald Haller; Lionel Dufayard; Praveen Vedagarbha; Trung Lang; Dean Lewis

ISTFA 2003; 371-377https://doi.org/10.31399/asm.cp.istfa2003p0371

View Articletitled, Laser Stimulation Applied to Dynamic IC Diagnostics

Speed Path Analysis: A Connection Between Speed Degradation, Silicon Dislocations, and Light Induced Voltage Alteration

D. Davis

ISTFA 2003; 378-383https://doi.org/10.31399/asm.cp.istfa2003p0378

View Articletitled, Speed Path Analysis: A Connection Between Speed Degradation, Silicon Dislocations, and Light Induced Voltage Alteration

Fault Localization of a Scan Shift Problem on Integrated Logic Designs

C. Burmer; P. Egger; A. Huber; H. Cerva; D. Petit; F. Grellner

ISTFA 2003; 384-390https://doi.org/10.31399/asm.cp.istfa2003p0384

View Articletitled, Fault Localization of a Scan Shift Problem on Integrated Logic Designs

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

Michael B. Schmidt; Noor Jehan Saujauddin

ISTFA 2003; 391-396https://doi.org/10.31399/asm.cp.istfa2003p0391

View Articletitled, Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

Scanning Probe Microscopy

Quantitative Interpretation of Scanning Capacitance Microscope Images as Two-Dimensional Dopant Profiles

J. J. Kopanski; J. F. Marchiando

ISTFA 2003; 398-405https://doi.org/10.31399/asm.cp.istfa2003p0398

View Articletitled, Quantitative Interpretation of Scanning Capacitance Microscope Images as Two-Dimensional Dopant Profiles

Advanced Analysis of Thin and Ultrathin SiO₂ Films and SiO₂/Si Interfaces with Combined Atomic Force Microscopy Methods

Werner Frammelsberger; Guenther Benstetter; Thomas Schweinboeck; Richard Stamp; Janice Kiely

ISTFA 2003; 406-412https://doi.org/10.31399/asm.cp.istfa2003p0406

View Articletitled, Advanced Analysis of Thin and Ultrathin SiO<sub>2</sub> Films and SiO<sub>2</sub>/Si Interfaces with Combined Atomic Force Microscopy Methods

Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

Jon C. Lee; J. H. Chuang

ISTFA 2003; 413-418https://doi.org/10.31399/asm.cp.istfa2003p0413

View Articletitled, Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

Characterization of Interconnect Defects Due to Electromigration Using Scanning Thermal Microscopy

E.X.W. Wu; X.H. Zheng; J.C.H. Phang; L.J. Balk; J.R. Lloyd

ISTFA 2003; 419-424https://doi.org/10.31399/asm.cp.istfa2003p0419

View Articletitled, Characterization of Interconnect Defects Due to Electromigration Using Scanning Thermal Microscopy

Optoelectronic Devices

Failure Analysis of Vertical Cavity Surface Emission Laser Diodes

F. Siegelin; C. Brillert

ISTFA 2003; 426-430https://doi.org/10.31399/asm.cp.istfa2003p0426

View Articletitled, Failure Analysis of Vertical Cavity Surface Emission Laser Diodes

Indium Tin Oxide (ITO) Film Removal Technique for Failure Analysis on Packaged Optoelectronic Devices

Shawn Elliott; Jean Gordon; Peter Plourde

ISTFA 2003; 431-435https://doi.org/10.31399/asm.cp.istfa2003p0431

View Articletitled, Indium Tin Oxide (ITO) Film Removal Technique for Failure Analysis on Packaged Optoelectronic Devices

Discretes

MIM Capacitor Reliability Fault Identification Using IR Microthermography and Automated De-processing: A Case Study

J. Steele; T. Remmel; S. Wilson; M. Nair; P. Sanders; S. Kiefer; M. Sutton; W. Paulson; S. Bigelow; D. Qualls; D. Gajewski; M. Martin; J. Walls

ISTFA 2003; 437-439https://doi.org/10.31399/asm.cp.istfa2003p0437

View Articletitled, MIM Capacitor Reliability Fault Identification Using IR Microthermography and Automated De-processing: A Case Study

Magnetic Emission Mapping for Passive Integrated Components Characterisation

O. Crépel; Y. Bouttement; P. Descamps; C. Goupil; P. Perdu; R. Desplats; F. Beaudoin; M. Guirardel

ISTFA 2003; 440-445https://doi.org/10.31399/asm.cp.istfa2003p0440

View Articletitled, Magnetic Emission Mapping for Passive Integrated Components Characterisation

Yield Enhancement

Failure Analysis Case Study in 0.18μm Flash Memory Devices and Root Cause Identification

Wen-Rong Chen; Mao-Sheng Wu; Chi-Ling Chu

ISTFA 2003; 471-477https://doi.org/10.31399/asm.cp.istfa2003p0471

View Articletitled, Failure Analysis Case Study in 0.18μm Flash Memory Devices and Root Cause Identification

Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects

Terence Kane; Michael P. Tenney; John Bruley

ISTFA 2003; 478-484https://doi.org/10.31399/asm.cp.istfa2003p0478

View Articletitled, Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects

Volume Information

Credits

ISTFA 2003; iii-viihttps://doi.org/10.31399/asm.cp.istfa2003fm01

View Articletitled, Credits

Preface

ISTFA 2003; xhttps://doi.org/10.31399/asm.cp.istfa2003fm02

View Articletitled, Preface

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