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ISTFA 2000

November 12–16, 2000

Bellevue, Washington, USA

Conference Sponsors:

Electronic Device Failure Analysis Society
ASM International

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis

Issue navigation

IPFA Best Paper Award Winner
Advanced Techniques
Packaging
Test/Yield
Poster Session
Backside
EOS/ESD
Techniques
Case Histories
Packaging
Case Histories
Packaging
Case Histories
FIB
Discretes
Techniques
Case Histories
Scanning Probe Microscopy
Backside
Volume Information

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis

IPFA Best Paper Award Winner

Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors

Wai Mun Yee; Mario Paniccia; Travis Eiles; Valluri Rao

ISTFA 2000; 3-8https://doi.org/10.31399/asm.cp.istfa2000p0003

View Articletitled, Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors

Advanced Techniques

Scanning Electron Acoustic Microscopy: A Novel Tool for Failure Analysis and Microcharacterization

W-K Wong; J.T.L. Thong; J.C.H. Phang; Q.R. Yin; J.W. Fang

ISTFA 2000; 11-16https://doi.org/10.31399/asm.cp.istfa2000p0011

View Articletitled, Scanning Electron Acoustic Microscopy: A Novel Tool for Failure Analysis and Microcharacterization

Application of Single Contact Optical Beam Induced Currents (SCOBIC) for Backside Failure Analysis

M. Palaniappan; J.M. Chin; J.C.H. Phang; D.S.H. Chan; C.E. Soh; G. Gilfeather

ISTFA 2000; 17-21https://doi.org/10.31399/asm.cp.istfa2000p0017

View Articletitled, Application of Single Contact Optical Beam Induced Currents (SCOBIC) for Backside Failure Analysis

Packaging

Measurement of Interfacial Adhesion and its Degradation in Multi-Layer Packages, Devices, and Blanket Films Using the Laser Spallation Technique

Vijay Gupta; Robert Hernandez; Rajen Dias; Vasudeva Atluri; George Raiser; Mike Mello; Lars Skoglund; Paul Zimmerman

ISTFA 2000; 25-33https://doi.org/10.31399/asm.cp.istfa2000p0025

View Articletitled, Measurement of Interfacial Adhesion and its Degradation in Multi-Layer Packages, Devices, and Blanket Films Using the Laser Spallation Technique

New FIB-Supported Approach for Wire-Bondpad Characterization

Peter Jacob; Giovanni Nicoletti

ISTFA 2000; 35-40https://doi.org/10.31399/asm.cp.istfa2000p0035

View Articletitled, New FIB-Supported Approach for Wire-Bondpad Characterization

Failure Analysis of Flip-Chip Bumps After Thermal Stressing

Tejpal K. Hooghan; Kultaransingh Hooghan; Sho Nakahara; Robert K. Wolf; Robert W. Privette; Ralph S. Moyer

ISTFA 2000; 41-48https://doi.org/10.31399/asm.cp.istfa2000p0041

View Articletitled, Failure Analysis of Flip-Chip Bumps After Thermal Stressing

X-Ray Tomography for Electronic Packages

Deepak Goyal

ISTFA 2000; 49-54https://doi.org/10.31399/asm.cp.istfa2000p0049

View Articletitled, X-Ray Tomography for Electronic Packages

Electronic Package Failure Analysis Using TDR

Dima A. Smolyansky

ISTFA 2000; 277-283https://doi.org/10.31399/asm.cp.istfa2000p0277

View Articletitled, Electronic Package Failure Analysis Using TDR

Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool

Damion T. Searls; Anura Don; Emilie Dy; Deepak Goyal

ISTFA 2000; 285-291https://doi.org/10.31399/asm.cp.istfa2000p0285

View Articletitled, Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool

Contrast Inversions in Scanning Acoustic Microscopy (C-SAM) of Glue Die-Attach

Boris Plikat

ISTFA 2000; 293-302https://doi.org/10.31399/asm.cp.istfa2000p0293

View Articletitled, Contrast Inversions in Scanning Acoustic Microscopy (C-SAM) of Glue Die-Attach

Application of Scanning Acoustic Microscopy to Electric and Electronic Parts

C. Miyasaka; B. R. Tittmann

ISTFA 2000; 303-306https://doi.org/10.31399/asm.cp.istfa2000p0303

View Articletitled, Application of Scanning Acoustic Microscopy to Electric and Electronic Parts

Failure Analysis of Stacked-Chip Scale Package

Christopher C. Flores

ISTFA 2000; 333-337https://doi.org/10.31399/asm.cp.istfa2000p0333

View Articletitled, Failure Analysis of Stacked-Chip Scale Package

Reducing Top-of-Die Plastic Delamination by Assuring Pre-Mold Cleanliness of Die Surfaces

R.K. Lowry; J.H. Linn; A.L. Northen; J.R. Zalnoski; H.W. Satterfield

ISTFA 2000; 339-345https://doi.org/10.31399/asm.cp.istfa2000p0339

View Articletitled, Reducing Top-of-Die Plastic Delamination by Assuring Pre-Mold Cleanliness of Die Surfaces

SMT Ceramic Capacitor Failure Mechanisms, Isolation Tools, Techniques and Analysis Methods

Ralph A. Carbone; David J. Roche

ISTFA 2000; 347-353https://doi.org/10.31399/asm.cp.istfa2000p0347

View Articletitled, SMT Ceramic Capacitor Failure Mechanisms, Isolation Tools, Techniques and Analysis Methods

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

George M. Wenger; Richard J. Coyle; Patrick P. Solan; John K. Dorey; Courtney V. Dodd; Anthony Primavera; Robert Erich

ISTFA 2000; 355-366https://doi.org/10.31399/asm.cp.istfa2000p0355

View Articletitled, Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

Test/Yield

Data Analysis Tools and Methodologies for Quick Yield Learning in a High Volume Manufacturing Environment

L. Andrade; T. Taylor

ISTFA 2000; 57-62https://doi.org/10.31399/asm.cp.istfa2000p0057

View Articletitled, Data Analysis Tools and Methodologies for Quick Yield Learning in a High Volume Manufacturing Environment

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

Y. N. Hua; Z. R. Guo; L. H. An; Shailesh Redkar

ISTFA 2000; 63-68https://doi.org/10.31399/asm.cp.istfa2000p0063

View Articletitled, Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement

Cary A. Gloor

ISTFA 2000; 69-75https://doi.org/10.31399/asm.cp.istfa2000p0069

View Articletitled, Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

Srikanth Perungulam; Scott Wills; Greg Mekras

ISTFA 2000; 77-79https://doi.org/10.31399/asm.cp.istfa2000p0077

View Articletitled, Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

Julie Segal; Arman Sagatelian; Bob Hodgkins; Tom Ho; Ben Chu; Tony Singh; Harvey Berman

ISTFA 2000; 81-85https://doi.org/10.31399/asm.cp.istfa2000p0081

View Articletitled, In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

Poster Session

Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

J. N. C. de Luna; M. O. del Fierro; J. L. Muñoz

ISTFA 2000; 89-91https://doi.org/10.31399/asm.cp.istfa2000p0089

View Articletitled, Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology

Song Zhigang; Loh Sock Khim; Shailesh Redkar

ISTFA 2000; 93-95https://doi.org/10.31399/asm.cp.istfa2000p0093

View Articletitled, Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology

Forensic Microscopy in the Failure Analysis Laboratory

William E. Vanderlinde; David A. Stoney

ISTFA 2000; 97-105https://doi.org/10.31399/asm.cp.istfa2000p0097

View Articletitled, Forensic Microscopy in the Failure Analysis Laboratory

Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device

Steve Hsiung; Victer Chan

ISTFA 2000; 107-115https://doi.org/10.31399/asm.cp.istfa2000p0107

View Articletitled, Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device

A Study on the Yield Loss Due to Al(Cu) Interconnections with Spacing Failure

Ruey Lian Hwang; Yung-Sheng Huang; Ying-Lang Wang; Ming-Jer Lee

ISTFA 2000; 117-120https://doi.org/10.31399/asm.cp.istfa2000p0117

View Articletitled, A Study on the Yield Loss Due to Al(Cu) Interconnections with Spacing Failure

Near IR Absorption in Heavily Doped Silicon – An Empirical Approach

R. Aaron Falk

ISTFA 2000; 121-123https://doi.org/10.31399/asm.cp.istfa2000p0121

View Articletitled, Near IR Absorption in Heavily Doped Silicon – An Empirical Approach

Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement

Jean-Yves Glacet; Fourmun Lee

ISTFA 2000; 129-135https://doi.org/10.31399/asm.cp.istfa2000p0129

View Articletitled, Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement

LSI Process Diagnosis for High Reliability Usage

Miki Imai; Daiki Tanaka; Katsuhiko Hosoda; Katsuhumi Noda; Sumio Matsuda

ISTFA 2000; 137-140https://doi.org/10.31399/asm.cp.istfa2000p0137

View Articletitled, LSI Process Diagnosis for High Reliability Usage

Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection

Fred Y. Chang; Victer Chan

ISTFA 2000; 141-146https://doi.org/10.31399/asm.cp.istfa2000p0141

View Articletitled, Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection

UV Reflectance Spectroscopy of the Copper/Copper Oxide System for Assessment of Solderability

L. S. Forney; C. Thierolf; B. Toleno; G. Parks

ISTFA 2000; 147-151https://doi.org/10.31399/asm.cp.istfa2000p0147

View Articletitled, UV Reflectance Spectroscopy of the Copper/Copper Oxide System for Assessment of Solderability

Backside

Antireflection Coatings for Semiconductor Failure Analysis

Brennan Davis; Wilson Chi

ISTFA 2000; 155-160https://doi.org/10.31399/asm.cp.istfa2000p0155

View Articletitled, Antireflection Coatings for Semiconductor Failure Analysis

Comparative Study of Sample Preparation Techniques for Backside Analysis

Philippe Perdu; Romain Desplats; Felix Beaudoin

ISTFA 2000; 161-171https://doi.org/10.31399/asm.cp.istfa2000p0161

View Articletitled, Comparative Study of Sample Preparation Techniques for Backside Analysis

A Comparison of Backside Emission Microscopy Systems

Brennan V. Davis

ISTFA 2000; 173-176https://doi.org/10.31399/asm.cp.istfa2000p0173

View Articletitled, A Comparison of Backside Emission Microscopy Systems

Failure Analysis from the Backside of a Die

Silke Liebert

ISTFA 2000; 177-185https://doi.org/10.31399/asm.cp.istfa2000p0177

View Articletitled, Failure Analysis from the Backside of a Die

Transparent Heat Spreader for Backside Optical Analysis of High Power GHz-Scale Microprocessors

Travis M. Eiles; Dean Hunt; David Chi

ISTFA 2000; 547-551https://doi.org/10.31399/asm.cp.istfa2000p0547

View Articletitled, Transparent Heat Spreader for Backside Optical Analysis of High Power GHz-Scale Microprocessors

New Laser Ablation Method for Non-Destructive Backside Sample Preparation

F. Beaudoin; P. Perdu; F. Saviot; D. Lewis; F. Salin

ISTFA 2000; 553-558https://doi.org/10.31399/asm.cp.istfa2000p0553

View Articletitled, New Laser Ablation Method for Non-Destructive Backside Sample Preparation

Silicon Trenching Using Dry Etch Process for Backside FIB and Probing

Valentina Korchnoi; Amos Fenigstein; Anastasia Barger

ISTFA 2000; 559-565https://doi.org/10.31399/asm.cp.istfa2000p0559

View Articletitled, Silicon Trenching Using Dry Etch Process for Backside FIB and Probing

Application of Near IR, Phase-Contrast Imaging to Backside Failure Isolation and Analysis

R. Aaron Falk; Edward W. Budiarto

ISTFA 2000; 567-573https://doi.org/10.31399/asm.cp.istfa2000p0567

View Articletitled, Application of Near IR, Phase-Contrast Imaging to Backside Failure Isolation and Analysis

EOS/ESD

ESD Effects on Electromigration Performance of Aluminum Metallization Systems

J. E. Vinson; M. J. Dion

ISTFA 2000; 189-194https://doi.org/10.31399/asm.cp.istfa2000p0189

View Articletitled, ESD Effects on Electromigration Performance of Aluminum Metallization Systems

Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring

Michael Fliesler; Ian H. Morgan

ISTFA 2000; 195-201https://doi.org/10.31399/asm.cp.istfa2000p0195

View Articletitled, Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring

Transmission Line Pulse Testing of the ESD Protection Structures in ICs – A Failure Analyst’s Perspective

Leo G. Henry; Jon Barth; John Richner; Koen Verhaege

ISTFA 2000; 203-213https://doi.org/10.31399/asm.cp.istfa2000p0203

View Articletitled, Transmission Line Pulse Testing of the ESD Protection Structures in ICs – A Failure Analyst’s Perspective

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

Amy Poe; Steve Brockett; Tony Rubalcava

ISTFA 2000; 215-221https://doi.org/10.31399/asm.cp.istfa2000p0215

View Articletitled, Failure Analysis of CDM-ESD Damage in a GaAs RFIC

Techniques

A Focused Ion Beam Technique to Electrically Contact the Deep Trench Capacitor of a Single Active Memory Cell in the Sub 0.25µm Technology Regime

Gunnar Zimmermann; Mark Johnston; Rolf Christ

ISTFA 2000; 225-230https://doi.org/10.31399/asm.cp.istfa2000p0225

View Articletitled, A Focused Ion Beam Technique to Electrically Contact the Deep Trench Capacitor of a Single Active Memory Cell in the Sub 0.25µm Technology Regime

The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures

Mark Morris; James Mohr; Esteban Ortiz; Steven Englebretson

ISTFA 2000; 231-234https://doi.org/10.31399/asm.cp.istfa2000p0231

View Articletitled, The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures

Selective Au Etching in Au/Al Bonds in Current IC Technology

M. Vanzi; A. Serpe; E.F. Trogu; P. Deplano; C. Hartfield; W. Subido

ISTFA 2000; 235-239https://doi.org/10.31399/asm.cp.istfa2000p0235

View Articletitled, Selective Au Etching in Au/Al Bonds in Current IC Technology

A Novel Method to Analyze the Deep Trench Capacitors in DRAM

Jack Lee; Kuo-Hui Huang; Jen-Lang Lue

ISTFA 2000; 241-244https://doi.org/10.31399/asm.cp.istfa2000p0241

View Articletitled, A Novel Method to Analyze the Deep Trench Capacitors in DRAM

Planar TEM Analysis of Nanoindented Samples Using the Focused Ion Beam Lift-Out Technique

T. L. Shofner; S. R. Brown; B.B. Rossie; M. A. Decker; Y. S. Obeng; F. A. Stevie; J.L. Drown

ISTFA 2000; 459-461https://doi.org/10.31399/asm.cp.istfa2000p0459

View Articletitled, Planar TEM Analysis of Nanoindented Samples Using the Focused Ion Beam Lift-Out Technique

Computerized Quantification of the Dicing Process: The First Step Toward Related Die Cracking Failure Analysis

Doug Glover; John R. Lynch; Irvin Huseby

ISTFA 2000; 463-467https://doi.org/10.31399/asm.cp.istfa2000p0463

View Articletitled, Computerized Quantification of the Dicing Process: The First Step Toward Related Die Cracking Failure Analysis

Automatic IC Die Positioning in the SEM

H.W. Tan; J.C.H Phang; J.T.L Thong

ISTFA 2000; 469-477https://doi.org/10.31399/asm.cp.istfa2000p0469

View Articletitled, Automatic IC Die Positioning in the SEM

Integrated Circuit Waveform Probing Using Optical Phase Shift Detection

Ken Wilsher; William Lo; Travis M. Eiles; Guoqing Xiao

ISTFA 2000; 479-485https://doi.org/10.31399/asm.cp.istfa2000p0479

View Articletitled, Integrated Circuit Waveform Probing Using Optical Phase Shift Detection

Case Histories

Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor

Jim B. Colvin; Anirban Roy

ISTFA 2000; 247-249https://doi.org/10.31399/asm.cp.istfa2000p0247

View Articletitled, Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor

Thermal Fatigue Induced Voiding in LDMOS Transistors Submitted to Multiple Energy Discharges

I. Percheron-Garcon; J.M. Bosc; C. Levade; M. Cabié; G. Vanderschaeve

ISTFA 2000; 255-262https://doi.org/10.31399/asm.cp.istfa2000p0255

View Articletitled, Thermal Fatigue Induced Voiding in LDMOS Transistors Submitted to Multiple Energy Discharges

Humidity-Bias Driven Shorts in Multilayer Circuits: A Case Study in Failure Analysis

Hei-Ruey Harry Jen; Gerald S. D’Urso; Harold Andrews

ISTFA 2000; 263-266https://doi.org/10.31399/asm.cp.istfa2000p0263

View Articletitled, Humidity-Bias Driven Shorts in Multilayer Circuits: A Case Study in Failure Analysis

Passivation Cracks in a Four-Level Metal Low-K Dielectric Backend Process

Michael C. Olewine; John F. DiGregorio; Gus J. Colovos; Kevin F. Saiz; Hongjiang Sun

ISTFA 2000; 267-277https://doi.org/10.31399/asm.cp.istfa2000p0267

View Articletitled, Passivation Cracks in a Four-Level Metal Low-K Dielectric Backend Process

Combining FIB Sequential Cross-Sectioning with TEM for Small Defect Analysis in SRAM Array

Nathan Wang; Rei Fang

ISTFA 2000; 309-313https://doi.org/10.31399/asm.cp.istfa2000p0309

View Articletitled, Combining FIB Sequential Cross-Sectioning with TEM for Small Defect Analysis in SRAM Array

Failure Analysis of Tungsten Stud Defect from the CMP Process

K. Takagi; Y. Kohno; S. Nukii

ISTFA 2000; 315-321https://doi.org/10.31399/asm.cp.istfa2000p0315

View Articletitled, Failure Analysis of Tungsten Stud Defect from the CMP Process

Integrated Circuit SNR Improvement Using Dielectric Altering Compound, Laser Trim and FIB System

B.J. Dutt; J.J. Kroutch, Jr.; K.N. Hooghan; R.J. Jenkins; M.J. Toth

ISTFA 2000; 323-326https://doi.org/10.31399/asm.cp.istfa2000p0323

View Articletitled, Integrated Circuit SNR Improvement Using Dielectric Altering Compound, Laser Trim and FIB System

Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs

T. Kane; M. Cambra; M. Tenney; P. McGinnis; A. Domenicucci; Y. Wang; D. Falcon

ISTFA 2000; 327-330https://doi.org/10.31399/asm.cp.istfa2000p0327

View Articletitled, Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs

Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing

Y. N. Hua; E. C. Low; L. H. An; Shailesh Redkar

ISTFA 2000; 369-372https://doi.org/10.31399/asm.cp.istfa2000p0369

View Articletitled, Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing

High Temperature Solder (Au/Sn) Failures from Nickel Plating Impurities

Carl B. Bunis

ISTFA 2000; 373-376https://doi.org/10.31399/asm.cp.istfa2000p0373

View Articletitled, High Temperature Solder (Au/Sn) Failures from Nickel Plating Impurities

Semiconductor Wear Out at Nuclear Power Plants

James B. Riddle

ISTFA 2000; 377-383https://doi.org/10.31399/asm.cp.istfa2000p0377

View Articletitled, Semiconductor Wear Out at Nuclear Power Plants

UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies

Timothy C. Wilkins

ISTFA 2000; 385-389https://doi.org/10.31399/asm.cp.istfa2000p0385

View Articletitled, UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies

Failure Analysis of MEMS Using Thermally-Induced Voltage Alteration

Jeremy A. Walraven; Edward I. Cole, Jr.; Paiboon Tangyunyong

ISTFA 2000; 489-496https://doi.org/10.31399/asm.cp.istfa2000p0489

View Articletitled, Failure Analysis of MEMS Using Thermally-Induced Voltage Alteration

Application of TIVA in Design Debug

Siva Kolachina; Bill Taylor; Kendall Scott Wills; Edward I. Cole, Jr.

ISTFA 2000; 497-501https://doi.org/10.31399/asm.cp.istfa2000p0497

View Articletitled, Application of TIVA in Design Debug

Backside Fault Isolation Using a Magnetic Field Imaging System on SRAMs with Indirect Shorts

L. A. Knauss; B. M. Frazier; A. B. Cawthorne; E. Budiarto; R. Crandall; S. Melnik; C. Bennett

ISTFA 2000; 503-507https://doi.org/10.31399/asm.cp.istfa2000p0503

View Articletitled, Backside Fault Isolation Using a Magnetic Field Imaging System on SRAMs with Indirect Shorts

FIB

Wafer Conserving Full Range Construction Analysis for IC Fabrication and Process Development Based on FIB/Dual Beam Inline Application

R. Weiland; C. Boit; B. Ebersberger; P. Meis; N. Dawes; A. Dziesiaty; H. Zimmermann; E. Demm; A. Hirsch; L. Frey; C. Lehrer; S. Geyer; M. Kamolz; H. Rettenmaier; W. Tittes; H. Lezec; R. Treichler

ISTFA 2000; 393-396https://doi.org/10.31399/asm.cp.istfa2000p0393

View Articletitled, Wafer Conserving Full Range Construction Analysis for IC Fabrication and Process Development Based on FIB/Dual Beam Inline Application

Focused Ion Beam Analysis of Low-K Dielectrics

H. J. Bender; R. A. Donaton

ISTFA 2000; 397-405https://doi.org/10.31399/asm.cp.istfa2000p0397

View Articletitled, Focused Ion Beam Analysis of Low-K Dielectrics

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

Romain Desplats; Timothee Dargnies; Jean-Christophe Courrege; Philippe Perdu; Jean-Louis Noullet

ISTFA 2000; 407-414https://doi.org/10.31399/asm.cp.istfa2000p0407

View Articletitled, Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications

Raghaw S. Rai; Swaminathan Subramanian; Stewart Rose; James Conner; Phil Schani; Jamey Moss

ISTFA 2000; 415-421https://doi.org/10.31399/asm.cp.istfa2000p0415

View Articletitled, Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications

Discretes

EOS Simulation and Failure Analysis of Metallurgically Bonded Silicon Diodes

Alexander Teverovsky

ISTFA 2000; 425-434https://doi.org/10.31399/asm.cp.istfa2000p0425

View Articletitled, EOS Simulation and Failure Analysis of Metallurgically Bonded Silicon Diodes

Temperature Distributions in III-V and SiC Micro-Wave Power Transistors Using Spatially Resolved Photoluminescence and Raman-Spectrometry Mapping Respectively

P. Martin; R. Bisaro; C. Dua; O. Noblanc; S. L. Delage; D. Floriot; F. Lemaire; P. Galtier; J. P. Landesman; C. Brylinski

ISTFA 2000; 435-442https://doi.org/10.31399/asm.cp.istfa2000p0435

View Articletitled, Temperature Distributions in III-V and SiC Micro-Wave Power Transistors Using Spatially Resolved Photoluminescence and Raman-Spectrometry Mapping Respectively

Failure Analysis of a Transistor Lead

Yasushi Deguchi; Sumio Matsuda; Jiro Aoki; Takashi Tamura; Yasunobu Iwai; Shigeki Kikui

ISTFA 2000; 443-448https://doi.org/10.31399/asm.cp.istfa2000p0443

View Articletitled, Failure Analysis of a Transistor Lead

Liquid Metal Embrittlement of Copper Wires

L. E. Brown

ISTFA 2000; 449-455https://doi.org/10.31399/asm.cp.istfa2000p0449

View Articletitled, Liquid Metal Embrittlement of Copper Wires

Scanning Probe Microscopy

Local Electrical Thickness-Mapping of Thin Oxides with Conducting Atomic Force Microscopy

Alexander Olbrich; Bernd Ebersberger; Christian Boit

ISTFA 2000; 511-519https://doi.org/10.31399/asm.cp.istfa2000p0511

View Articletitled, Local Electrical Thickness-Mapping of Thin Oxides with Conducting Atomic Force Microscopy

Guidelines for Two-Dimensional Dopant Profiling Using Scanning Capacitance Microscopy

Axel Born; R. Wiesendanger

ISTFA 2000; 521-527https://doi.org/10.31399/asm.cp.istfa2000p0521

View Articletitled, Guidelines for Two-Dimensional Dopant Profiling Using Scanning Capacitance Microscopy

pn Junction Delineation in Si Devices Using Scanning Capacitance Spectroscopy

Hal Edwards

ISTFA 2000; 529-532https://doi.org/10.31399/asm.cp.istfa2000p0529

View Articletitled, pn Junction Delineation in Si Devices Using Scanning Capacitance Spectroscopy

Contactless Voltage and Current Contrast Imaging with Scanning Force Microscope Based Test Systems

W. Mertin; S.-W. Bae; U. Behnke; R. Weber; E. Kubalek

ISTFA 2000; 533-543https://doi.org/10.31399/asm.cp.istfa2000p0533

View Articletitled, Contactless Voltage and Current Contrast Imaging with Scanning Force Microscope Based Test Systems

Volume Information

Credits

ISTFA 2000; iv-viiihttps://doi.org/10.31399/asm.cp.istfa2000fm01

View Articletitled, Credits

Preface

ISTFA 2000; xiiihttps://doi.org/10.31399/asm.cp.istfa2000fm02

View Articletitled, Preface

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