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integrated circuits
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Series: ASM Handbook
Volume: 13C
Publisher: ASM International
Published: 01 January 2006
DOI: 10.31399/asm.hb.v13c.a0004172
EISBN: 978-1-62708-184-9
...Abstract Abstract In a typical semiconductor integrated circuits (SICs) component, corrosion may be observed at the chip level and at the termination area of the lead frames that are plated with a solderable metal or alloy, such as tin and tin-lead alloys that are susceptible to corrosion...
Abstract
In a typical semiconductor integrated circuits (SICs) component, corrosion may be observed at the chip level and at the termination area of the lead frames that are plated with a solderable metal or alloy, such as tin and tin-lead alloys that are susceptible to corrosion. This article focuses on the key factors contributing to corrosion of electronic components, namely, chemicals (salts containing halides, sulfides, acids, and alkalis), temperature, air (polluted air), moisture, contact between dissimilar metals in a wet condition, applied potential differences, and stress. It discusses the chip corrosion and oxidation of tin and tin-lead alloys (solders) in SIC. The article also addresses the corrosion of the device terminations resulting in lead (termination) tarnishing that are caused by various factors, including galvanic corrosion, chemical residues, base metal migration and plating additives.
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Published: 01 January 1986
Fig. 12 Auger images from the area of the integrated circuit shown in Fig. 11 . (a) Silicon oxide. (b) Elemental silicon. (c) Oxygen. (d) Aluminum. Source: Ref 20
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Published: 01 August 2018
Fig. 27 Typical ceramic-packaged integrated circuit showing the silicon die, which is bonded to the metallized surface
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Published: 01 August 2018
Fig. 34 Integrated circuit (IC) bonded to a frame of tiny leads that have been simultaneously bonded by a process known as tape automated bonding. This process is being used to perform interconnections on densely packed ICs having over 300 leads per chip.
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Image
Published: 01 August 2018
Fig. 6 Different gray-scale images of an integrated circuit (IC) module on a printed circuit board. (a) Binary. (b) 8-level gray scale. (c) 64-level gray scale. Courtesy of Cognex Cooperation
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Series: ASM Handbook
Volume: 2
Publisher: ASM International
Published: 01 January 1990
DOI: 10.31399/asm.hb.v02.a0001091
EISBN: 978-1-62708-162-7
... temperatures. This article discusses the uses of gallium in optoelectronic devices and integrated circuits and applications of gallium. The article discusses the properties and grades of gallium arsenide and also provides information on resources of gallium. The article talks about the recovery techniques...
Abstract
Gallium-base components can be found in a variety of products ranging from compact disk players to advanced military electronic warfare systems, owing to the factor that it can emit light, has a greater resistance to radiation and operates at faster speeds and higher temperatures. This article discusses the uses of gallium in optoelectronic devices and integrated circuits and applications of gallium. The article discusses the properties and grades of gallium arsenide and also provides information on resources of gallium. The article talks about the recovery techniques, including recovery from bauxite, zinc ore and secondary recovery process and purification. The article briefly describes the fabrication process of gallium arsenide crystals. Furthermore, the article gives a short note on world supply and demand of gallium and concludes with research and development on gallium arsenide integrated circuits.
Book Chapter
Book: Fractography
Series: ASM Handbook
Volume: 12
Publisher: ASM International
Published: 01 January 1987
DOI: 10.31399/asm.hb.v12.a0000631
EISBN: 978-1-62708-181-8
... the atomic oxygen environment exposure effect, solar cell interconnect, integrated circuit defects, and fatigue failure of these materials. electronic materials fatigue failure fractograph integrated circuits ultrasonic cleaning Fig. 1326, 1327 Effect of exposure to the atomic oxygen...
Abstract
This article is an atlas of fractographs that helps in understanding the causes and mechanisms of fracture of electronic materials, including L-shaped electronic flat pack, transistor base lead, ohmic contact window, and brush/slip ring assembly. The fractographs illustrate the atomic oxygen environment exposure effect, solar cell interconnect, integrated circuit defects, and fatigue failure of these materials.
Book: Casting
Series: ASM Handbook
Volume: 15
Publisher: ASM International
Published: 01 December 2008
DOI: 10.31399/asm.hb.v15.a0005209
EISBN: 978-1-62708-187-0
...Abstract Abstract One impressive example of plane front solidification (PFS) is the industrial production of large silicon single crystals, used mainly as substrates for integrated circuits. This article explores the PFS of a single phase, without taking convection into account. It discusses...
Abstract
One impressive example of plane front solidification (PFS) is the industrial production of large silicon single crystals, used mainly as substrates for integrated circuits. This article explores the PFS of a single phase, without taking convection into account. It discusses the solute build-up at the solid-liquid interface forming transients and steady state, the morphological stability/instability and perturbation theory, and rapid solidification effects, including solute trapping and oscillatory instabilities. The article presents a microstructural selection map that presents an overview of interface stability as a function of composition for a given alloy.
Book: Surface Engineering
Series: ASM Handbook
Volume: 5
Publisher: ASM International
Published: 01 January 1994
DOI: 10.31399/asm.hb.v05.a0001285
EISBN: 978-1-62708-170-2
... enhancement of the CVD process is discussed briefly. The article also describes the properties of amorphous and crystalline films deposited by the PECVD process for integrated circuit fabrication. amorphous silicon films dielectric films integrated circuit fabrication microelectronic device...
Abstract
This article discusses the application of amorphous and crystalline films through plasma-enhanced chemical vapor deposition (PECVD) from the view point of microelectronic device fabrication. It describes the various types of PECVD reactors and deposition techniques. Plasma enhancement of the CVD process is discussed briefly. The article also describes the properties of amorphous and crystalline films deposited by the PECVD process for integrated circuit fabrication.
Series: ASM Handbook
Volume: 6
Publisher: ASM International
Published: 01 January 1993
DOI: 10.31399/asm.hb.v06.a0001459
EISBN: 978-1-62708-173-3
...Abstract Abstract Soldering technology has been used in applications ranging from the packaging of integrated circuit chips to the fabrication of industrial heat exchangers and consequently in structural or electronic applications. This article provides information on various soldering...
Abstract
Soldering technology has been used in applications ranging from the packaging of integrated circuit chips to the fabrication of industrial heat exchangers and consequently in structural or electronic applications. This article provides information on various soldering parameters, including types of solder alloy in terms of selection process; selection of substrate base material; flux selection based on adequate wettability by the solder; solder joint assembly; combined substrate, solder, and flux properties; and manufacturing procedures. Each of these parameters is explored using examples of both structural and electronic applications. The article concludes with a discussion on the environmental, safety, and health issues to be considered during soldering.
Series: ASM Handbook
Volume: 6
Publisher: ASM International
Published: 01 January 1993
DOI: 10.31399/asm.hb.v06.a0001460
EISBN: 978-1-62708-173-3
...Abstract Abstract Soldering represents the primary method of attaching electronic components, such as resistors, capacitors, or packaged integrated circuits, to either printed wiring board whose defects is minimized by consideration of proper PWB design, device packages, and board assembly...
Abstract
Soldering represents the primary method of attaching electronic components, such as resistors, capacitors, or packaged integrated circuits, to either printed wiring board whose defects is minimized by consideration of proper PWB design, device packages, and board assembly. This article discusses the categories that are most important to successful electronic soldering, namely, solders and fluxes selection, nature of base materials and finishes, solder joint design, and solderability testing.
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Published: 01 January 1986
Fig. 11 Secondary electron micrograph of crystalline structure on an integrated circuit. Source: Ref 20
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Published: 01 December 2004
Fig. 38 Laboratory x-ray image of a six-layer copper interconnect structure in an integrated circuit. The smallest features on the chip are about 160 nm in size and are easily resolved by the system with ∼80 nm resolution.
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Published: 01 August 2018
Fig. 35 Scanning laser acoustic microscopy image at 200 MHz of tape-automated-bonded leads on an integrated circuit. The bright areas at the tips of each lead indicate good-quality bonds. Field of view: 1.75 × 1.3 mm
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Published: 01 August 2018
Fig. 32 C-mode scanning acoustic microscopy reflection-mode image at 15 MHz of a plastic-encapsulated integrated circuit showing a suspicious area of the lead frame. In this image, the brightness of the image (toward white) represents the magnitude of the echoes from the interface
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Published: 01 August 2018
Fig. 9 Comparison of acoustic microscopy applications with C-scan applications, based on transducer frequency and wavelength. C-SAM, C-mode scanning acoustic microscopy; SLAM, scanning laser acoustic microscopy; SAM, scanning acoustic microscopy; NDT, nondestructive testing; IC, integrated
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Published: 01 August 2018
Fig. 38 Pulse-echo scanning acoustic micrograph of 4 to 6 μm (160 to 240 μin.) wide aluminum lines on the silicon substrate of an integrated circuit. Dark spots are silicon nodule defects, the source of which is silicon bubbling up from the substrate of the wafer. Courtesy of G.H. Thomas, Sandia
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Published: 01 August 2018
Fig. 31 Schematic illustrating use of the C-mode scanning acoustic microscopy reflection technique to evaluate the die-attach bond between the silicon die and the ceramic package of a ceramic dual in-line package integrated circuit. With this technique, the ultrasound access to the bond layer
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Published: 01 December 1998
Fig. 5 Scanning Auger mapping of elements, including some of low atomic number, in a foreign particle on an integrated circuit. Note also the ability to distinguish between elemental silicon and silicon oxide due to bonding effects on Auger energies. (a) Secondary electron image of particle. (b-e
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Published: 01 August 2018
unsharpness ( Eq 11 ) is minimized, as shown by an integrated circuit magnified at (b) 1.25×, (c) 20×, and (d) 40×. Courtesy of Rockwell International
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