Since the introduction of chip scale packages (CSPs) in the early 90s, they have continuously increased their market share due to their advantages of small form factor, cost effectiveness and PCB optimization. The reduced package size brings challenges in performing failure analysis. This article provides an overview of CSPs and their classification as well as their advantages and applications, and reveals some of the challenges in performing failure analysis on CSPs, particularly for CSPs in special package configurations such as stacked die multi-chip-packages (MCPs) and wafer level CSPs (WLCSPs). The discussion covers special requirements of CSPs such as precision...
Susan Xia Li, Chip-Scale Packaging and Its Failure Analysis Challenges, Microelectronics Failure Analysis: Desk Reference, 7th ed., Edited By Tejinder Gandhi, ASM International, 2019, p 16–24, https://doi.org/10.31399/asm.tb.mfadr7.t91110016
Download citation file: