Section 7: Memory Failure Analysis
This article provides an introduction to the dynamic random access memory (DRAM) operation with a focus to localization techniques of the defects combined with some physical failure analysis examples and case studies for memory array failures. It discusses the electrical measurement techniques for array failure analysis. The article then presents know-how-based analysis techniques of array failures by bitmap classification. The limits of bitmapping that lead to well-known localization techniques like thermally induced voltage alteration and optical beam induced resistance change are also discussed. The article concludes by providing information on soft defect localization techniques.
Semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This article discusses five key disciplines of the signature analysis process that need to be orchestrated within the organization: design for test practices, test floor data collection methodology, post-test data analysis tools, root cause theorization, and physical failure analysis strategies.