This article provides an introduction to the dynamic random access memory (DRAM) operation with a focus to localization techniques of the defects combined with some physical failure analysis examples and case studies for memory array failures. It discusses the electrical measurement techniques for array failure analysis. The article then presents know-how-based analysis techniques of array failures by bitmap classification. The limits of bitmapping that lead to well-known localization techniques like thermally induced voltage alteration and optical beam induced resistance change are also discussed. The article concludes by providing information on soft defect localization techniques.
Martin Versen, DRAM Failure Analysis and Defect Localization Techniques, Microelectronics Failure Analysis: Desk Reference, 7th ed., Edited By Tejinder Gandhi, ASM International, 2019, p 499–505, https://doi.org/10.31399/asm.tb.mfadr7.t91110499
Download citation file: