The ratio of good to bad die on a production wafer can range from less than 10% to well over 90%, depending on the process and the complexity of the design. This article provides an overview of the modeling approaches used to predict wafer yield. It explains how to account for relative circuit complexity, systematic and random defects, and defect clustering. As the examples in the article show, with just a basic understanding of yield models, readers can estimate expected yield losses and identify abnormal yield results for a given design.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This article presents an automation workflow for the development of analog and mixed-signal devices similar to the two-stage process used for the design and verification of logic ICs. The use of a co-simulation interface makes it possible to build and verify failure models.

Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

This column suggests that developing 3D structural models as tools for observing and exploring failures in the virtual domain could prove instrumental in avoiding failure without committing hardware. Likewise, instead of building hardware to systematically evaluate failures in the presence of random effects, virtualization through a 3D model could provide a completely user-defined environment for conducting controlled experiments. In such a virtual environment, systematic and random behaviors can be introduced and parsed to provide greater clarity in the search for root causes of failure.

Root-cause analysis and FA work hand-in-hand to identify the source of a problem, gather relevant data, and resolve the issue. However, even experienced professionals can succeed in FA while failing in the outcome. This article explains how to avoid common traps, dead ends, and faulty thought processes in the search for root causes.

This is the second of a two-article series that presents a complete business model for Failure Analysis (FA) as a high tech provider in the world of microelectronics. Part I introduced the fundamentals of such a model. It started with the definitions of a business process, and then the analysis flows were presented. Finally, a Key Performance Indicator (KPI) based operation was developed. Part II handles the implementation of such a model in an FA lab. It discusses the interdependencies of workload and cycle time, in other words the pipeline management. This opens the path to quantitative target setting agreements with customers. A complete system builds a database that can calculate all the parameters for a FA lab tailored exactly to the demand of the customer. Such a database acts as a reference lab and defines best FA practice.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design.

Thermally-induced voltage alteration (TIVA) is a laser-based method for localizing interconnect defects in ICs. Its main limitation is that the laser must heat the defect and change its resistance sufficiently to produce a measurable voltage alteration. Anything that interferes with laser absorption or alters defect heating makes TIVA less effective. This article presents the results of a study on the effects of local structures on TIVA imaging. The authors selected a polysilicon-metal test structure as the focal point of their study, which entailed experimental investigation along with modeling and simulation. It was found that the TIVA profiles on this structure are strongly influenced by local geometry, particularly the variation of interlevel silicon dioxide thickness and the placement of polysilicon lines with respect to aluminum lines. Understanding such relationships is essential for locating defects using TIVA techniques.

Scanning microwave impedance microscopy (sMIM) is a relatively new method for making electrical measurements on test samples in AFMs. This article presents examples in which sMIM technology is used to measure dielectric coefficients, doping concentrations, and nanoscale C-V curves for different semiconductor and dielectric materials. It also explains how measured results compare with theoretical models, confirming the validity of each approach.

Scanning microwave impedance microscopy (sMIM) is an electrical measurement technique that can be used to determine dopant profiles in semiconductor devices. This article describes the basic setup and implementation of the method and demonstrates its use in the cross-sectional analysis of NMOS power transistors.

This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.

This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

The market for semiconductor manufacturing equipment has consolidated rapidly over the last decade; where there were once hundreds of potential customers, there are now perhaps a dozen in the first tier. This transformation has been driven primarily by the dramatic growth in the cost and complexity of the manufacturing process and has caused a shift in the priorities that guide purchasing decisions—from technical performance to asset utilization. These changes are also reflected in the failure analysis (FA) lab, where rising tool costs and operator expertise requirements have made it increasingly difficult to justify the investment required to maintain a complete state-of-the-art capability. Outsourcing some FA activity has become increasingly attractive.

This article presents the results of a study conducted at Sandia National Labs to assess the effect of electrostatic discharge on surface micromachined MEMS devices. This failure mode has largely been overlooked because ESD failure mechanisms often mimic the effects of stiction-adhesion. To measure the susceptibility of MEMS devices to ESD, Sandia engineers built and tested a silicon microengine and a torsional ratcheting microactuator. Test results indicate that the effects of ESD are highly dependent on device design, component stiffness, and geometry and that slight modifications can bring improvements.

A string of failures discovered during final testing after assembly led analysts on a long search for the cause, which turned out to be an unusual form of electrostatic discharge (ESD). Most ESD impacts on ICs occur by way of the pins. Nearly all ESD models, including the widely used human body model, charged-device model, and machine model, are based on this assumption. However, as this case study proves, passivated wafers and unpackaged dies are also susceptible to ESD damage. The authors explain that although this type of failure is difficult to diagnose, they were able to pinpoint the cause using lock-in microthermography and rule out mechanical-, FIB-, and laser-induced failures, which are similar in appearance.

At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it.