A team of semiconductor engineers recently developed a new fault localization method tailored for high-resistance faults. In this article, they discuss the basic principle of the technique and explain how they validated it for various test cases.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.

This column explains that in order for supply chain partners to optimize quality and end-to-end yield, progress must be made in the areas of embedded instrument standards, test access mechanisms, and traceability.

Designing circuit edits at the contact level offers tremendous advantages in reliability and yield success over similar edits designed in the metal stack. To that end, a full-thickness backside circuit edit strategy has been developed that eliminates part thinning and promotes the implementation of all edits at the contact level to avoid milling into the metal layers. This article describes the FIB-based circuit edit process and presents several case studies demonstrating its use on 65 nm technology devices.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

This columnn explores the idea that insights into the root cause of increasingly complex failures may be hidden in unanswered questions from past analyses, indicating that there might be more value in previous files than once thought.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

IDDQ testing is normally the key to isolating state-dependent defects in dense ICs. In the case study presented here, however, the functionally failing ICs did not fail the static IDDQ test nor did they draw significant current when biased into a static state on the lab bench. After extensive testing and analysis, including ATE IDDQ scanning, ATE-interfaced photo-emission microscopy, FIB assisted mechanical microprobing, and scanning capacitance microscopy, the defect was found to be p-type counterdoping of the n-active regions caused by a contaminated solvent tank used during wafer fabrication.

This column discusses the basic knowledge and skills needed by failure analysis engineers, with a focus on problem-solving ability.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Stress voiding has re-emerged as a concern in advanced metal systems with their reduced dimensions and multilayer designs. Unless analysts are familiar with the physics and history of stress voids in ICs, chances are they will go unnoticed. This article discusses the basic cause of stress cracks and the clues that give them away.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

Resistive interconnections, a type of soft failure, are extremely difficult to find using existing backside methods, and with flip-chip packages, alternative front side approaches are of little or no help. In an effort to address this challenge, a team of engineers developed a new method that uses the effects of resistive heating to directly locate defective vias, contacts, and conductors from either side of the die. In this article, they discuss the basic principles of their new method and demonstrate its use on two ICs in which a variety of resistive interconnection failures were found.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

This article explains how oxide traps and mobile ions can lead to timing and function failures in ICs and provides insights and advice on how to identify and deal with potential problems.

Failure analysis requires a working knowledge of physics, technology, materials, manufacturing practices, analytical techniques, and more. It is difficult to imagine what failure analysis would be like if all the laws of physics were perfectly apparent and all the challenges of sample preparation and testing were removed. Eliminating those considerations, failure analysis would be more like Sudoku. Sudoku is a simple number puzzle enjoyed by both children and adults. The simplicity of Sudoku compared to failure analysis is the point. Although Sudoku is starkly simple, the process is challenging to the best of us. Good and bad problem-solving practices are clearly exposed by the experience of solving a few Sudoku puzzles. Some insights that are brilliantly clear in Sudoku are equally true in failure analysis.