This article explains how laser voltage probing (LVP) can be used to analyze combinational logic circuits. The authors describe how the technique is aided by the development and use of a waveform library and a corresponding truth table. They also present a case study in which the new technique is used to isolate faults in a combinational logic circuit consisting of multiple gates.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

A scanning electron microscope system measures voltage contrast on device-under-test surfaces. This article addresses a limited set of applications that rely on voltage contrast (VC) measurements in SEM systems, showing how VC measurements can probe electrical activity running at speeds as high as 2 GHz on modern active integrated circuits.

Time domain reflectometry (TDR) is widely used to measure the electrical length of conductors. It has also proven useful for isolating failures in ICs. This article describes a variation of the method, called comparative TDR, that overcomes inherent timing limitations and simplifies use. It discusses the basic hardware requirements of the new technique and presents examples demonstrating its use on opens and shorts in ceramic flip-chip packages.

Differential laser voltage probe simultaneously acquires waveform data from a single target while the device under test fluctuates between passing and failing test outcomes. This article describes the use of this technique and how it could be affected by trends in the microelectronics industry.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

Laser voltage probing (LVP), an IR-based technique, facilitates through-silicon signal waveform acquisition and high frequency timing measurements from active p-n junctions on CMOS ICs. The ICs can be in flip-chip as well as wire-bond packages with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations.

Laser-assisted device alteration (LADA) is an effective tool for identifying speed-limiting paths in ICs. When implemented with a continuous wave laser, it can reveal where the speed-limiting path resides but not when the slow (or fast) logic transition is occurring. To overcome this limitation, an enhanced version of the technique has been developed. This article discusses the capabilities of the new method, called picosecond time-resolved LADA, and explains how it complements the existing failure analysis toolset, facilitating faster resolution of issues and root-cause identification.

This article discusses the concept of a virtual known good device (VKGD) and how it used in the development of advanced 3D packaging. It explains that a VKGD is essentially an electromagnetic model of an IC package, including bumps, interposers, and through-silicon vias. These models, used in conjunction with reflectometry data, help engineers isolate faults in the early stages of IC package development, greatly reducing cycle times.

This article discusses the challenges involved in testing analog and mixed-signal ICs and provides practical guidance and insights on how to deal with them.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

This article explains how the success rate of in-line scan chain logic macros can be nearly doubled for certain types of failures with the help of laser voltage imaging and laser voltage probing. The authors provide background information on LVI, LVP, and scan chain logic macros and show how they are used to diagnose skip test, clock-type, and soft single-latch failures.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

Advancements in photodetector technology are revitalizing time-resolved emission (TRE) techniques in semiconductor failure analysis. In this article, the authors explain how superconducting single-photon detectors improve the capabilities of TRE measurements as demonstrated on 14 nm FinFET technology and an inverter chain with power supply voltages down to 0.4 V.

Voltage contrast, a phenomenon that occurs in scanning electron microscopes, produces brightness variations in SEM images that correspond to potential variations on the test sample. Through appropriate processing, voltage contrast signals can reveal an extensive amount of information about the functionality of ICs. Voltage contrast can be used, for example, to map electrical logic levels and timing waveforms from internal nodes of the chip as it operates inside the SEM chamber. This article describes the fundamentals of voltage contrast and its applications in IC failure analysis.

This article discusses the basic principles of terahertz time-domain spectroscopy (THz-TDS) and the function and limitations of key components in a THz-TDS system. It also provides examples of some of the ways THz-TD imaging is used alone and in combination with other analytical techniques.

This article reviews the basic principles of scanning acoustic microscopy (SAM) and presents several case studies demonstrating its use in failure analysis and counterfeit detection. The FA case studies show how SAM is used to detect delamination, cracking, and manufacturing defects in ceramic chip capacitors and resistors, voids in a full-bridge rectifier, and a radiation-induced defect in a microprocessor. In cases involving counterfeit ICs, CSAM images reveal the presence of an abnormality on component packages, evidence of relabeling, and popcorn fractures indicative of the use of excessive heat and force to dislodge components from circuit board assemblies.

Conventional backside imaging takes advantage of silicon’s transmission of light which, based on the Plank relation ( E g = hc/ λ ), occurs at wavelengths greater than 1 µm. Because of diffraction, the lateral spatial resolution of backside imaging techniques is limited to about half the wavelength of the light source used, which is far too coarse to isolate faults in a typical IC. In this article, the authors explain how they overcome this limitation by reprofiling the backside of the silicon, forming spherically shaped domes. The raised convex surfaces act as solid immersion lenses that are shown to improve spatial resolution by nearly an order of magnitude. The degree of improvement is evaluated using backside emission microscopy (EMS), optical beam induced current (OBIC) imaging, and laser voltage probing (LVP) and the results are presented in the article.

This article describes a form of lock-in thermography that achieves 3D localization of thermally active defects in stacked die packages. In this approach, phase shifts associated with thermal propagation delay are analyzed as a function of frequency. This allows for a precise localization of defects in all three spatial dimensions and can serve as a guide for subsequent high-resolution physical analyses.

The analysis of scan-based ICs is essentially split between two domains: that of the designer and that of the device analyst. Designers tend to operate within the confines of fault characterization, looking for defects within logic blocks or structures based on test data. Device analysts, on the other hand, are more concerned with physical aspects of the defect such as location, composition, and morphology. These separate worlds are beginning to merge, however, as this case study shows, streamlining the entire failure analysis and resolution process.