Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

IDDQ testing is normally the key to isolating state-dependent defects in dense ICs. In the case study presented here, however, the functionally failing ICs did not fail the static IDDQ test nor did they draw significant current when biased into a static state on the lab bench. After extensive testing and analysis, including ATE IDDQ scanning, ATE-interfaced photo-emission microscopy, FIB assisted mechanical microprobing, and scanning capacitance microscopy, the defect was found to be p-type counterdoping of the n-active regions caused by a contaminated solvent tank used during wafer fabrication.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

The introduction of ultralow-k dielectrics is a recent milestone in the quest for higher clock speeds and lower power consumption in ICs. One tradeoff, however, is that interconnect stacks layered with low-k materials rather than SiO 2 are more vulnerable to mechanical damage. This article presents a method that makes it possible to assess the mechanical integrity of interconnect stacks at the wafer level. The new bump-assisted BEOL stability indentation (BABSI) test uses a nanoindentation tool to apply lateral and vertical forces to solder bumps and copper pillars on the wafer surface. By applying appropriate stresses, various aspects of integrity, such as the onset of failure modes or the weakest interface in the stack, can be determined by subsequent SEM/FIB analysis. The authors describe the basic principles of the measurement technique and some of the applications in which it was used.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This article addresses the considerations related to the development and introduction of new materials in response to the increasing performance demands of microelectronic devices, and how these new materials will affect characterization and failure analysis. The article is largely extracted from the “Deprocessing/Inspection White Paper” generated by the SEMATECH Product Analysis Forum (PAF), with updates from the PAF response to the International Technology Roadmap for Semiconductors.

Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance structure under which different physical mechanisms exhibit varying sensitivities to site-to-site, wafer-to-wafer, and lot-to-lot variations. This article uses Monte Carlo simulations to explore the impacts these hierarchical variance components can exert on perceptions of WET performance.

This article discusses the basic principles of SEM-based cathodoluminescence (CL) spectroscopy and demonstrates its usefulness in process development, statistical process control, and failure analysis. The technologies where the benefits of CL spectroscopy are most evident are compound semiconductor optoelectronics and high electron mobility transistors as reflected in the application examples.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

Integrated circuits are subjected to various forms of friction during fabrication and packaging, creating potential problems due to the buildup of charge. This article looks at the distinct characteristics of triboelectric charging damage on silicon-on-insulator devices at the wafer and package level. Telltale signs of this type of damage include spatial dependency, distinct TIVA-signal patterns, and bimodal static current distributions with significant changes after burn-in.

Root-cause analysis and FA work hand-in-hand to identify the source of a problem, gather relevant data, and resolve the issue. However, even experienced professionals can succeed in FA while failing in the outcome. This article explains how to avoid common traps, dead ends, and faulty thought processes in the search for root causes.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

This column explains that in order for supply chain partners to optimize quality and end-to-end yield, progress must be made in the areas of embedded instrument standards, test access mechanisms, and traceability.

A string of failures discovered during final testing after assembly led analysts on a long search for the cause, which turned out to be an unusual form of electrostatic discharge (ESD). Most ESD impacts on ICs occur by way of the pins. Nearly all ESD models, including the widely used human body model, charged-device model, and machine model, are based on this assumption. However, as this case study proves, passivated wafers and unpackaged dies are also susceptible to ESD damage. The authors explain that although this type of failure is difficult to diagnose, they were able to pinpoint the cause using lock-in microthermography and rule out mechanical-, FIB-, and laser-induced failures, which are similar in appearance.

This article discusses the primary differences between electrostatic discharge (ESD) and electrical overstress (EOS) and the circumstances under which they occur. It also explains how to differentiate ESD from EOS during failure analysis and how to avoid common misunderstandings and mistakes.

Secondary ion mass spectrometry (SIMS) works by bombarding the surface of a solid sample with ions, freeing charged atomic and molecular species which are then collected and analyzed. This article explains that SIMS has the ability to detect all elements in the periodic table in addition to inherent depth profiling capabilities, making it an indispensable tool for the characterization and analysis of semiconductor components and materials. It also presents several application examples.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

Resistive interconnections, a type of soft failure, are extremely difficult to find using existing backside methods, and with flip-chip packages, alternative front side approaches are of little or no help. In an effort to address this challenge, a team of engineers developed a new method that uses the effects of resistive heating to directly locate defective vias, contacts, and conductors from either side of the die. In this article, they discuss the basic principles of their new method and demonstrate its use on two ICs in which a variety of resistive interconnection failures were found.