This article presents an automation workflow for the development of analog and mixed-signal devices similar to the two-stage process used for the design and verification of logic ICs. The use of a co-simulation interface makes it possible to build and verify failure models.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

Counterfeit electronic parts have become a significant cause of concern in the electronics part supply chain. Several factors that contribute to the targeting of the electrical, electronic, and electromechanical (EEE) parts market by counterfeiters include parts obsolescence, extended lead times, the absence of verification tools, the availability of scrapped or salvaged parts, and the high costs associated with inspection/testing procedures. This article reports on the status of efforts by the G-19 Committee of SAE International to develop standards in response to increasing numbers of counterfeit parts in the supply chain.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

This article presents a failure analysis workflow tailored for complex ICs and device packages. The FA flow determines the root cause of failures using nondestructive analysis and advanced sample preparation techniques. The nondestructive tests typically used are X-ray radiography, scanning acoustic microscopy, time domain reflectometry, and magnetic current imaging. To gain access to interconnect failures, laser ablation is used, typically in combination with chemical etching to finish the decapsulation process. Repackaging is also part of the FA flow and is briefly discussed.

The curve tracer is a versatile lab instrument that can provide electrical characterization data for a variety of analyses. A curve tracer helped analyze a ceramic capacitor identifying leakage sites, acceleration factors, radiation sensitivity, and failure mechanism.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

This column reports on efforts by the SAE G-19A committee to develop an aerospace industry standard on practices to detect suspect counterfeit components, maximize the use of authentic parts, and ensure consistency across the supply chain for test techniques and requirements.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

Scanning microwave impedance microscopy (sMIM) is an electrical measurement technique that can be used to determine dopant profiles in semiconductor devices. This article describes the basic setup and implementation of the method and demonstrates its use in the cross-sectional analysis of NMOS power transistors.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

This column discusses the potential benefits of developing a dedicated synchrotron-based tool suite for advanced, high-throughput characterization, deprocessing, and validation of ICs.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

This article presents a complete business model for Failure Analysis (FA) as a high tech provider in the world of microelectronics. Part I introduces the fundamentals of such a model. It starts with the definitions of a business process, and then the analysis flows are presented. Finally, a Key Performance Indicator (KPI) based operation is developed. Part II of this article will appear in the next issue of EDFA, and it will address the implementation of such a model in an FA lab. It discusses the interdependencies of workload and cycle times—the pipeline management. This opens the path to quantitative target setting agreements with customers. A complete system builds a database that can calculate all the parameters for an FA lab tailored exactly to the demand of the customer. Such a database acts as a reference lab and represents best FA practice.