This article provides insights into the nature of IDDQ and timing defects and the challenges they present to failure analysts based on the findings of a Sematach study.

Time-resolved emission (TRE) systems are used in many FA labs for internal timing analysis of digital ICs. In this article, the authors explain how they use TRE systems to diagnose analog circuit failures as well. The key to their success is the use of an asynchronous trigger on the emission detector, which eliminates measurement error due to nonlinear distortion. A case study of an analog amplifier failure caused by a polysilicon short demonstrates the effectiveness of their technique.

Laser-assisted device alteration (LADA) is an effective tool for identifying speed-limiting paths in ICs. When implemented with a continuous wave laser, it can reveal where the speed-limiting path resides but not when the slow (or fast) logic transition is occurring. To overcome this limitation, an enhanced version of the technique has been developed. This article discusses the capabilities of the new method, called picosecond time-resolved LADA, and explains how it complements the existing failure analysis toolset, facilitating faster resolution of issues and root-cause identification.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

Atomic force microscopy has been a consistent factor in the advancements of the past decade in IC nanoprobing and failure analysis. Over that time, many new atomic force measurement techniques have been adopted by the IC analysis community, including scanning conductance, scanning capacitance, pulsed current-voltage, and capacitance-voltage spectroscopy. More recently, two new techniques have emerged: diamond probe milling and electrostatic force microscopy (EFM). As the authors of the article explain, diamond probe milling using an atomic force microscope is a promising new method for in situ, localized, precision delayering of ICs, while active EFM is a nondestructive alternative to EBAC microscopy for localization of opens in IC analysis.

Laser voltage probing (LVP), an IR-based technique, facilitates through-silicon signal waveform acquisition and high frequency timing measurements from active p-n junctions on CMOS ICs. The ICs can be in flip-chip as well as wire-bond packages with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations.

This article presents a complete business model for Failure Analysis (FA) as a high tech provider in the world of microelectronics. Part I introduces the fundamentals of such a model. It starts with the definitions of a business process, and then the analysis flows are presented. Finally, a Key Performance Indicator (KPI) based operation is developed. Part II of this article will appear in the next issue of EDFA, and it will address the implementation of such a model in an FA lab. It discusses the interdependencies of workload and cycle times—the pipeline management. This opens the path to quantitative target setting agreements with customers. A complete system builds a database that can calculate all the parameters for an FA lab tailored exactly to the demand of the customer. Such a database acts as a reference lab and represents best FA practice.

This is the second of a two-article series that presents a complete business model for Failure Analysis (FA) as a high tech provider in the world of microelectronics. Part I introduced the fundamentals of such a model. It started with the definitions of a business process, and then the analysis flows were presented. Finally, a Key Performance Indicator (KPI) based operation was developed. Part II handles the implementation of such a model in an FA lab. It discusses the interdependencies of workload and cycle time, in other words the pipeline management. This opens the path to quantitative target setting agreements with customers. A complete system builds a database that can calculate all the parameters for a FA lab tailored exactly to the demand of the customer. Such a database acts as a reference lab and defines best FA practice.

This article presents a failure analysis workflow tailored for complex ICs and device packages. The FA flow determines the root cause of failures using nondestructive analysis and advanced sample preparation techniques. The nondestructive tests typically used are X-ray radiography, scanning acoustic microscopy, time domain reflectometry, and magnetic current imaging. To gain access to interconnect failures, laser ablation is used, typically in combination with chemical etching to finish the decapsulation process. Repackaging is also part of the FA flow and is briefly discussed.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

The causes of failure in flip-chip packaged devices are often found at the interface between the die and package. Exposing the site of interest usually entails some form of mechanical cross-sectioning with the sample embedded in an epoxy puck. This article brings attention to some of the drawbacks with the current approach and presents a solution in the form of a redesigned puck. As test results show, the new puck significantly reduces polishing time, and when cast with a conductive epoxy, minimizes charging artifacts and image distortion during SEM analysis. It also facilitates easy sample removal for subsequent analysis.

A new way to detect gate oxide defects has been developed. The method, as the article explains, is based on wet chemical etching and is particularly effective for devices with floating gates. Test samples with exposed poly-Si gates are placed in a KOH:H 2 O solution and a voltage is applied to the silicon substrate. At a certain voltage, normal gates begin to etch, while those shorted to the substrate through gate oxide defects develop an anodic oxide and thus remain unetched. This method has proven effective in assessing gate oxide integrity without direct observation of the oxide, which requires complicated deprocessing and a lot of time. It also reveals electrical characteristics of gate oxides that are difficult to identify by conventional physical analysis.

Passive voltage contrast (PVC) has traditionally been used by semiconductor engineers for end-of-line post-mortem analysis. PVC distinguishes between open and short structures and is both nondestructive and noncontact. When applied during process development for in-line characterization, it allows wafers to be examined at multiple points, where electrical probing might not be feasible. This provides feedback on the cumulative effect of the process on critical parameters such as oxide integrity and can reduce development cycle times because wafers do not have to be deprocessed in order to determine the exact location of failures. Two case studies are presented in this article, demonstrating the use of PVC in a process development environment.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Recent developments in two relatively new failure analysis techniques, Seebeck effect imaging (SEI) and thermally-induced voltage alteration (TIVA), have greatly improved their defect detection sensitivity and image acquisition times for localizing open and shorted interconnections. This article presents several examples demonstrating the enhanced capabilities of these two methods.

Scanning electron microscopes (SEMs) are the dominant tool for electronic device testing, failure analysis, and characterization. This status was not apparent, however, when the first commercial SEM, the Cambridge Stereoscan, appeared in 1963. A market survey by the manufacturer at that time predicted total sales of six to ten units worldwide. For the last four decades, SEMs have sold at an average rate of one unit every 24 hours, with two out of every three instruments destined for the semiconductor industry.

At the ISTFA ’99 event, the organizers arranged for the first time a panel discussion on failure analysis related purely to EOS/ESD issues. Each panelist presented their area of expertise followed by two hours of lively exchange with the attendees and among attendees. The panel discussed how to differentiate EOS and ESD failures. These failures are more critical with the industry move to submicron geometries and newer interconnect materials and other processing technologies, such as copper and flip-chip processing.

Voltage contrast, a phenomenon that occurs in scanning electron microscopes, produces brightness variations in SEM images that correspond to potential variations on the test sample. Through appropriate processing, voltage contrast signals can reveal an extensive amount of information about the functionality of ICs. Voltage contrast can be used, for example, to map electrical logic levels and timing waveforms from internal nodes of the chip as it operates inside the SEM chamber. This article describes the fundamentals of voltage contrast and its applications in IC failure analysis.