This is the second article in a two-part series on how to properly thin curved and highly warped die. Part I, published in the August 2015 issue of EDFA , introduces the concept of contour machining, a CNC technique driven by thickness measurement data, and describes a multistep grinding and lapping process along with the results. Part II covers the mechanical, physical, and mounting variables associated with thinning and polishing, giving particular attention to mounting procedures and their effect on surface profiles and thickness variations.

This article, the first in a multi-part series, describes how to finely control remaining silicon thickness (RST) through the correction of mechanical surface profiles using multipoint thickness measurements. It explains why multipoint thickness measurements are necessary and discusses the realities of silicon thickness measurements. With careful processing, cleaning, and RST measurements, samples can be reliably processed to a 50 μm thickness with a variation of +/- 2.5 μm across the majority of the die.

This article, the first in a two-part series, discusses the challenges of thinning highly warped die and explains how they can be overcome with contour machining driven by thickness measurements. The machine that was used measures die surface profiles in situ, producing a wire frame model by which it controls the rotation and movement of the tooling spindle. The thinning process used in this demonstration consists of a grinding step followed by several rounds of lapping, resulting in a uniform die thickness with minimal surface imperfections. The mechanical limitations of flattening a curved die in preparation for die thinning will be discussed in Part II of this article in the November 2015 issue of EDFA .

The processes and considerations for locally thinning an area of interest to the desired remaining silicon thickness are described.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

Acoustic microimaging has advanced over the past few years in response to the growing use of thinner silicon die and innovative packaging designs. This article reviews the basic principles of acoustic imaging technology and describes some of the applications made possible by improvements in spatial resolution, focal length, F-number, and water couplant temperature control. It also discusses common imaging challenges and explains how they can be resolved.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

Designing circuit edits at the contact level offers tremendous advantages in reliability and yield success over similar edits designed in the metal stack. To that end, a full-thickness backside circuit edit strategy has been developed that eliminates part thinning and promotes the implementation of all edits at the contact level to avoid milling into the metal layers. This article describes the FIB-based circuit edit process and presents several case studies demonstrating its use on 65 nm technology devices.

Engineers at Infineon Technologies have developed a way to detect probing-induced fracture in semiconductor wafers in real-time using acoustic emission sensing and burst-signal energy filtering techniques. In this article, they describe the measurement procedure and demonstrate its use on complex semiconductor pad stacks. They also present experimental results that shed new light on the relationship between probe tip contact force and crack probability in thin, brittle layers typical of BEOL layer stacks in CMOS ICs.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

This is the second article in a two-part series on the causes of stress voiding and the evidence required to tie it to an IC interconnect failure. The first part, published in the November 1999 issue of EDFA, focuses on the causes and distinguishing characteristics of stress void failures. Here, that information is applied in the analysis of an actual case of stress voiding. The author explains how he developed evidence of stress, nucleation, and diffusion, the three phenomena required to differentiate stress voiding from other failure mechanisms, and how this evidence pointed to specific processing errors and suggested how to fix them. Although the investigation relied heavily on traditional observational tools, they were applied in new ways using a relatively new technique, FIB backside thinning, to gain critical proof of nucleation and confirm suspected processing errors.

This article describes a sample preparation technique by which specific areas on integrated circuits can be manually polished to TEM transparency. The technique, called tripod polishing or the wedge method, produces cross-section samples within a few hours that require little or no additional thinning for TEM analysis. The method can also be used to prepare plan view TEM samples as well as samples for SEM analysis and light microscopy.

Improved X-ray detector technology continues to be a critical need in the semiconductor industry, particularly for high-spatial-resolution X-ray microanalysis using lowbeam-voltage field-emission scanning electron microscopes (FE-SEMs). In response to this need, a prototype microcalorimeter energy-dispersive spectrometer has been developed. This article discusses the capabilities of the new tool and demonstrates its use in thin-film and particle analysis. It also discusses ongoing development efforts and potential future advancements.

This article describes two innovative methods that can significantly improve the resolution of SEM imaging: scanning transmission electron microscopy in a scanning electron microscope (STEM-in-SEM) and forward-scattered electron imaging (FSEI). Both methods can be implemented in any SEM using special sample holders. No other modifications are required. Test results presented in the article show that 1 to 2 nm resolution is possible in thin sections, uncoated polysilicon gates, and photoresist.

A new and improved sample preparation technique was developed by Wang. This technique uses an FIB instrument for the 90° rotation of a small portion of the specimen on the original grid by taking advantage of static force. All sample preparation steps, including thin-section creation and sample tilting, can be accomplished in a single process. The procedure is monitored in a high-resolution FIB instrument to assure a 100% success rate. Figure 1 shows a scanning electron microscope image of a 3D TEM sample with two rotated sections. The original TEM sample is a lift-out sample laid on carbon film.

Failure analysts use a variety of machines for sample preparation, many of which are mechanical in nature. This article discusses the factors that determine the accuracy, resolution, and repeatability of XY positioning systems, rotary stages, and multiaxis machines. It identifies critical machine parameters and explains how environmental effects, runout, and geometric inaccuracies contribute to uncertainty and positioning error. It also assesses the precision, accuracy, and repeatability required for backside thinning and delayering systems.

Chip-level 3D integration, where chips are thinned, stacked, and vertically interconnected using TSVs and microbumps, brings as many challenges as it does improvements, particularly in the area of failure analysis. This article assesses the capabilities of various FA techniques in light of the challenges posed by 3D integration and identifies current shortcomings and future needs.

In this case study, the author describes the investigation of a defective DC-DC converter retrieved from an aircraft following the report of abnormal system behavior. Electrical testing, local probing, X-ray imaging, and cross-sectional analysis led to the discovery of cracks on several pins and in some of the solder material. The cracks were caused by different rates of thermal expansion and were remedied with the help of thermomechanical analysis, EBSD imaging, and phase map comparisons for thick and thin solder joints.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

Over the last few years, new challenges increased the pressure on packaging and assembly analytical resources. Reduced product development cycle time, increased market segmentation, new package and die level materials, ever shrinking device geometries, and fully enabled technologies (i.e. with thermal, retention, and EMI solutions) created these new pressures on fault isolation/failure analysis efforts and package development.