The ratio of good to bad die on a production wafer can range from less than 10% to well over 90%, depending on the process and the complexity of the design. This article provides an overview of the modeling approaches used to predict wafer yield. It explains how to account for relative circuit complexity, systematic and random defects, and defect clustering. As the examples in the article show, with just a basic understanding of yield models, readers can estimate expected yield losses and identify abnormal yield results for a given design.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

One of the co-chairs of the Case Histories sessions at ISTFA 2012 provides a summary of three papers that demonstrate a solid understanding of the semiconductor FA process. The first paper describes the investigation of fractures in PCB traces, the second paper presents a method for analyzing defects due to implanter charging effects, and the third paper explains how analysts determined the cause of automatic test pattern generation failures concentrated in certain areas of the wafer.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

The tools of the trade in semiconductor failure analysis have advanced rapidly over the past few decades, bringing major improvements in imaging, deprocessing, and materials analysis. In contrast to the progress made in physical FA, little attention has been given to the failure analysis process itself. This article shows through case studies how simple oversights and misunderstandings can lead to costly mistakes. It also defines basic FA concepts and presents a failure analysis sequence, describing each step along with common pitfalls and best practices.