Search Results for solid immersion lens

Backside optical analysis is often aided by solid immersion lenses (SILs), but as the authors of this article explain, SILs improve the resolution of front side thermography as well. The authors describe the physics behind solid immersion lenses and provide examples that demonstrate the advantages and limitations of their use from the font side.

The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

Conventional backside imaging takes advantage of silicon’s transmission of light which, based on the Plank relation ( E g = hc/ λ ), occurs at wavelengths greater than 1 µm. Because of diffraction, the lateral spatial resolution of backside imaging techniques is limited to about half the wavelength of the light source used, which is far too coarse to isolate faults in a typical IC. In this article, the authors explain how they overcome this limitation by reprofiling the backside of the silicon, forming spherically shaped domes. The raised convex surfaces act as solid immersion lenses that are shown to improve spatial resolution by nearly an order of magnitude. The degree of improvement is evaluated using backside emission microscopy (EMS), optical beam induced current (OBIC) imaging, and laser voltage probing (LVP) and the results are presented in the article.

Metrology targets are an essential tool for evaluating the performance of imaging systems and maintaining their accuracy over time. Ideally, the pattern on the target is simple enough that the expected image is intuitive or, at least, easily simulated. Although many such targets exist for frontside imaging, until recently, few if any could be found for backside applications. In this article, the first of a two-part series, the authors explain how they addressed this gap by converting a readily available frontside target for backside use. The conversion process is described step by step in enough detail that it can be replicated in order to convert other frontside targets. Due to the success of the converted target, an unmounted, backside-specific version has subsequently been developed, the availability of which not only eliminates one of the more difficult steps in the original conversion process, but also provides additional benefits. Using one of these newer targets, the authors evaluated a backside imaging system consisting of a laser scanning microscope (LSM) and a solid immersion lens (SIL). The results are presented here along with the criteria used for the evaluation. Other applications of the new metrology target as well as its limitations are discussed in the May 2015 issue of EDFA .

Researchers at Boston University have made significant improvements in the resolution that can be achieved with backside imaging techniques. In this article, they explain how they optimize lateral and longitudinal resolution of IR-based methods using aplanatic solid immersion lenses in combination with adaptive optics that correct for aberrations, interferometry to improve signal-to-noise ratios, vortex beams that overcome diffraction limitations, and image reconstruction techniques based on prior knowledge about the objects under investigation.

This article discusses the generation of heat that occurs in ICs during failure analysis and examines the effectiveness of various die cooling techniques including heat spreading films, spray cooling, and liquid and air jet impingement.

One of the pioneering developers of induced voltage alteration (IVA) measurement techniques assesses the current state of the technology, the impact of major advancements, and the potential for further improvements. The assessment pays particular attention to biasing approaches, phase-locked loop detection techniques, the effect of solid immersion lenses on spatial resolution, and the emergence of production-type sample preparation methods.

The shrinking geometries in today’s 3-D integrated circuit (IC) designs generate an urgent need for a variety of tools to isolate failures on advanced semiconductor devices. There has been no single technique that adequately addresses all types of failures with the required fast cycle time. Complex failures that are not resolved by the faster global approaches are best addressed by probing technologies, where waveforms or voltages are measured from node to node. These approaches are time-consuming and usually require detailed understanding of the circuit operation. Global techniques that map the secondary effects of defects have been widely used for as many failures as possible. These secondary effects include thermal emission, photon emission, and circuit operation dependencies on localized heating or carrier generation at a defect site. Each technique addresses some segment of the failure mechanisms, but none is universally effective in itself. The use of thermal emission techniques has waned due to the issues of lower power supply voltages, which result in poor sensitivity for older techniques and decrease in minimum resolved feature sizes.

This paper describes a methodology for preparing contoured devices by using a milling machine in conjunction with a spectral reflectance measurement system for meeting ±5 μm remaining silicon thickness (RST) tolerances.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

This column reviews a survey of the top ISTFA contributors from 1999 to 2008 and the topics addressed in their papers.

This article, the first in a two-part series, discusses the challenges of thinning highly warped die and explains how they can be overcome with contour machining driven by thickness measurements. The machine that was used measures die surface profiles in situ, producing a wire frame model by which it controls the rotation and movement of the tooling spindle. The thinning process used in this demonstration consists of a grinding step followed by several rounds of lapping, resulting in a uniform die thickness with minimal surface imperfections. The mechanical limitations of flattening a curved die in preparation for die thinning will be discussed in Part II of this article in the November 2015 issue of EDFA .

The second phase of the IARPA Circuit Analysis Tools (CAT) program, which ended in June 2015, focused on the development of prototype tools to demonstrate scalability to the 10 nm node. Our guest columnist, IARPA Program Manager, Carl E. McCants, provides a summary of what the participating teams accomplished.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

The semiconductor industry continues to scale microelectronics in accordance with Moore’s Law, as the minimum feature size on integrated circuits has decreased from 800 nm in 1993 to 90 nm in 2003 to 22 nm today. In addition, manufacturing advances include 3-D packaging, with multiple dice stacked in various configurations, and 3-D integrated circuits that use through-silicon vias or through-oxide vias to connect the various dice layers. The Intelligence Advanced Research Projects Activity (IARPA) Circuit Analysis Tools (CAT) program is developing tools and techniques to ensure that the U.S. government has capabilities for circuit analysis at future technology nodes, specifically at 22 nm and beyond, and for chips assembled using advanced packaging techniques. This column describes the CAT program activities and goals.

This is the second article in a two-part series that explains how to measure the performance of solid immersion lenses (SILs) used for backside imaging and analysis. In Part I, published in the February 2015 issue of EDFA , the authors describe how they modified a frontside metrology target and used it to evaluate a SIL in a backside imaging system, which prompted the development of an unmounted, backside-specific version of the through-silicon target. In Part II, they explain how these new targets, in addition to measuring resolution, are being used to determine the field of view as well as the line spread and edge response of backside imaging systems. They also discuss some of the challenges encountered when using the targets to characterize emission microscopy systems.

This article compiles summaries of User Group meetings held at ISTFA 2013, including the Contactless Fault Isolation User’s Group, the Focused Ion Beam User’s Group, the Sample Prep/3D Package User’s Group, and the Nanoprobing User’s Group. For each meeting, a brief synopsis of the presentations and subsequent dialog is provided.

This article demonstrates a simple and robust backside illumination method for infrared imaging of ICs. The technique uses oblique illumination, which removes surface noise components while providing bright-field illumination under the surface, and requires only modest if any polishing of the backside of the substrate. As the examples in the article show, it can be implemented with a standard microscope with IR optics, yielding high contrast, high resolution images without the need for complex lenses, AR coatings, or sophisticated scanning electronics.

The 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2011) was held October 3 to 7, 2011, in Bordeaux, France. The conference concentrated on two main areas in electronics that concern designers, manufacturers, and users: (1) strategy for quality and reliability assessment of electronic circuits and systems, and (2) advanced analysis techniques for technology and product evaluation. This article reports on highlights of the technical program.

Laser-assisted device alteration (LADA) is an effective tool for identifying speed-limiting paths in ICs. When implemented with a continuous wave laser, it can reveal where the speed-limiting path resides but not when the slow (or fast) logic transition is occurring. To overcome this limitation, an enhanced version of the technique has been developed. This article discusses the capabilities of the new method, called picosecond time-resolved LADA, and explains how it complements the existing failure analysis toolset, facilitating faster resolution of issues and root-cause identification.