Search Results for solder cracks

In this case study, the author describes the investigation of a defective DC-DC converter retrieved from an aircraft following the report of abnormal system behavior. Electrical testing, local probing, X-ray imaging, and cross-sectional analysis led to the discovery of cracks on several pins and in some of the solder material. The cracks were caused by different rates of thermal expansion and were remedied with the help of thermomechanical analysis, EBSD imaging, and phase map comparisons for thick and thin solder joints.

Failures of interest in this article usually occur on single-sided, non-plated-through-hole circuit boards. Evidence of failure may be as subtle as crazing (a pattern of small surface cracks) of solder-joint surfaces or as catastrophic as burning of the circuit board. Over time, crazing coalesces into circumferential cracks in the solder joint, and these cracks deepen until catastrophic failure occurs.

This article presents a method for determining the integrity of solder joints made from mixed and lead-free solders. It discusses the procedures involved in sample preparation and testing and explains how to interpret the results, particularly the effect intermetallic formation, cracking, and voiding.

Four panel members participated in the ISTFA 2014 Panel Discussion on the importance of correctly determining the cause of failure in electronic devices and systems designated for use in space, downhole drilling, and other such applications. Reliability of these components is critical because they cannot be easily replaced and malfunctions can be catastrophic. The panelists presented several methods for analyzing failures in integrated electrical systems and identifying the root cause.

With the July 2006 implementation of RoHS (the restriction of the use of certain hazardous substances in electrical and electronic equipment), the electronics reliability industry has seen a changeover to lead-free solders and “green” mold compounds that have no bromine- or antimony-based flame retardants. This article addresses some of the challenges caused by implementation of the new requirements.

Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

A deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy is presented.

One of the co-chairs of the Case Histories sessions at ISTFA 2012 provides a summary of three papers that demonstrate a solid understanding of the semiconductor FA process. The first paper describes the investigation of fractures in PCB traces, the second paper presents a method for analyzing defects due to implanter charging effects, and the third paper explains how analysts determined the cause of automatic test pattern generation failures concentrated in certain areas of the wafer.

This article presents best practices and procedures for analyzing printed circuit board assembly failures. It discusses the role of electrostatic discharge and electrical overstress, the increasing complexity of ball grid arrays and buried vias, the challenges associated with lead-free solder processes, and the problems caused by counterfeit components flowing into our supply lines. It also includes a summary of the tools available to failure analysts and how they are best put to use

This article explains how the failure of a high-voltage capacitor led to the discovery of an unusual defect. Testing showed that the capacitor shorted due to silver migration, which investigators believe was facilitated by voids in the dielectric that had been present from the time of manufacture. Through some combination of time, electric potential, trapped humidity, and elevated operating temperature, plate material migrated into the voids, creating a short path that led to the failure. Using acoustic images as a guide, the failed capacitor was cross-sectioned, allowing investigators to examine the voids more closely and thereby confirm their theory.

Electronic components and assemblies are subjected to temperature variations at every stage of life, resulting in the buildup of internal stress. This article explains how such stress contributes to failures and introduces a measurement technique that allows users to visualize stress distributions and assess their effects on lifetime and reliability. Application examples illustrating the capabilities of the new topography and deformation measurement approach are also presented.

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

The influence of electric current flow and electrically induced Joule heat on thermal stress for weld joint cracks at both interfaces is still not fully comprehended. This article investigates the effect of subjecting the ball grid array package to a cyclic current input. Current density, Joule effect, and temperature curves are examined.

This is the second article in a two-part series investigating solder connection failures associated with BGA packages. Part I, in the February 2017 issue of EDFA, examines various cases of open and short circuit failures, discusses the formation of voids, and explains how to reveal important clues by grinding away the BGA package. Part II continues the analysis of voids and focuses in on failures due to circuit board faults. In such cases, the board is ground away from the backside, stopping just short of the first inner copper layer. The alignment of the two uppermost copper layers, the integrity of microvias, and other potential problems are then examined using polarized light which readily passes through the remaining resin and fibers. As the examples in the article show, this approach can reveal a wide range of manufacturing defects in PCBs.

IBM engineers recently conducted a study to better understand and control the reliability of copper pillar solder joints in 2.5-D packages. Here they describe their approach and the results they obtained. They explain how they created test samples to evaluate different solder compositions, pillar geometries, and thermal histories and assess their effect on microstructure, precipitate morphology, intermetallic layer thickness, and shear strength. They also present thermal cycling test results comparing the performance of silicon and glass interposers.

The introduction of ultralow-k dielectrics is a recent milestone in the quest for higher clock speeds and lower power consumption in ICs. One tradeoff, however, is that interconnect stacks layered with low-k materials rather than SiO 2 are more vulnerable to mechanical damage. This article presents a method that makes it possible to assess the mechanical integrity of interconnect stacks at the wafer level. The new bump-assisted BEOL stability indentation (BABSI) test uses a nanoindentation tool to apply lateral and vertical forces to solder bumps and copper pillars on the wafer surface. By applying appropriate stresses, various aspects of integrity, such as the onset of failure modes or the weakest interface in the stack, can be determined by subsequent SEM/FIB analysis. The authors describe the basic principles of the measurement technique and some of the applications in which it was used.

This article describes the qualification process for a 1.8 kW laser diode stack designed for the Mars Curiosity rover. The seven-bar stack serves as the optical pump in a boom-mounted spectroscope attached to the front of the rover. Each laser bar is made of 62 single emitters and generates 260 W of instantaneous optical power. A detailed design analysis of the diode stack is presented along with the results of overstress testing and failure analysis.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques.

This article addresses the issue of capacitor failures, explaining how and why they occur and how to determine the cause. It describes the frequent but often overlooked reliability failure mechanisms of ceramic, foil, and electrolytic capacitors.

Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.