Search Results for solder balls

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

This is the second article in a two-part series investigating solder connection failures associated with BGA packages. Part I, in the February 2017 issue of EDFA, examines various cases of open and short circuit failures, discusses the formation of voids, and explains how to reveal important clues by grinding away the BGA package. Part II continues the analysis of voids and focuses in on failures due to circuit board faults. In such cases, the board is ground away from the backside, stopping just short of the first inner copper layer. The alignment of the two uppermost copper layers, the integrity of microvias, and other potential problems are then examined using polarized light which readily passes through the remaining resin and fibers. As the examples in the article show, this approach can reveal a wide range of manufacturing defects in PCBs.

A deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy is presented.

This article presents best practices and procedures for analyzing printed circuit board assembly failures. It discusses the role of electrostatic discharge and electrical overstress, the increasing complexity of ball grid arrays and buried vias, the challenges associated with lead-free solder processes, and the problems caused by counterfeit components flowing into our supply lines. It also includes a summary of the tools available to failure analysts and how they are best put to use

Electronic components and assemblies are subjected to temperature variations at every stage of life, resulting in the buildup of internal stress. This article explains how such stress contributes to failures and introduces a measurement technique that allows users to visualize stress distributions and assess their effects on lifetime and reliability. Application examples illustrating the capabilities of the new topography and deformation measurement approach are also presented.

With the July 2006 implementation of RoHS (the restriction of the use of certain hazardous substances in electrical and electronic equipment), the electronics reliability industry has seen a changeover to lead-free solders and “green” mold compounds that have no bromine- or antimony-based flame retardants. This article addresses some of the challenges caused by implementation of the new requirements.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques.

This article provides a summary of the presentations given at the four User’s Group meetings at ISTFA 2012. Each user group focused on one of the following topics: nanoprobing, contactless fault isolation, focused ion beam, and sample preparation.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques. It also includes a case study involving a failure caused by improper laser marking.

X-ray computed tomography is a noninvasive technique that can reveal the internal structure of objects in three dimensions with spatial resolution down to 50 nm. This article discusses the basic principles of this increasingly important imaging technology and presents examples of its use on various types of defects in semiconductor packages.

Over the last few years, new challenges increased the pressure on packaging and assembly analytical resources. Reduced product development cycle time, increased market segmentation, new package and die level materials, ever shrinking device geometries, and fully enabled technologies (i.e. with thermal, retention, and EMI solutions) created these new pressures on fault isolation/failure analysis efforts and package development.

Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.

This article, the first in a two-part series, discusses the challenges of thinning highly warped die and explains how they can be overcome with contour machining driven by thickness measurements. The machine that was used measures die surface profiles in situ, producing a wire frame model by which it controls the rotation and movement of the tooling spindle. The thinning process used in this demonstration consists of a grinding step followed by several rounds of lapping, resulting in a uniform die thickness with minimal surface imperfections. The mechanical limitations of flattening a curved die in preparation for die thinning will be discussed in Part II of this article in the November 2015 issue of EDFA .

This article presents two case histories that shed light on the role of gold in lead-free solder joint failures and the damage mechanisms involved. One of the failures, a brittle fracture of the solder joint, is attributed to the synergistic effects of voids, intermetallic compounds, and CTE mismatch. The investigation of the other failure revealed evidence of tin-whisker formation. As the author explains, the growth of tin whiskers is due to compressive stress in the tin solder material caused by diffusion of end-cap metals (Ni and Cu) and the formation of Sn-Ni-Au intermetallics. In both cases, the failures can be prevented by limiting the thickness of gold on all components.

This article presents a method for determining the integrity of solder joints made from mixed and lead-free solders. It discusses the procedures involved in sample preparation and testing and explains how to interpret the results, particularly the effect intermetallic formation, cracking, and voiding.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

Integrated circuits are subjected to various forms of friction during fabrication and packaging, creating potential problems due to the buildup of charge. This article looks at the distinct characteristics of triboelectric charging damage on silicon-on-insulator devices at the wafer and package level. Telltale signs of this type of damage include spatial dependency, distinct TIVA-signal patterns, and bimodal static current distributions with significant changes after burn-in.

Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.

This is the second article in a two-part series on how to properly thin curved and highly warped die. Part I, published in the August 2015 issue of EDFA , introduces the concept of contour machining, a CNC technique driven by thickness measurement data, and describes a multistep grinding and lapping process along with the results. Part II covers the mechanical, physical, and mounting variables associated with thinning and polishing, giving particular attention to mounting procedures and their effect on surface profiles and thickness variations.