Single contact optical beam induced currents (SCOBIC) is a variation on the OBIC failure analysis technique that requires only one point of contact with the junction being examined. This article discusses the basic principles of this new method and how it compares with OBIC in terms of measurement performance. It also presents examples showing how SCOBIC can be used to analyze CMOS devices from the front and back side without need for complex FIB and microprobing procedures.

This column provides a ten-year retrospective on laser-based fault isolation techniques and the important role of laser signal injection microscopes.

The power of scanning optical microscopes (SOMs) lies in their ability to direct a small spot of light into an IC, producing photocarriers and heat in a localized area of the circuit. Photonic and thermal energy affect the I-V characteristics of the circuit in different ways, depending on the presence of defects and local material properties. This article explains how light beams interact with semiconductors and metals and how they influence the I-V characteristic of circuits and devices. It describes the basic physics of SOM measurements, provides examples of static and dynamic SOM techniques, and discusses emerging applications.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

This column identifies promising new failure analysis technologies based on the papers published in recent ISTFA conferences. The purpose of the column is not to select the "best of the best," but rather to understand the technologies that have been developed and adopted to solve the ever-growing challenges in failure analysis.

The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

This article discusses the types of defects that occur in vertical cavity surface-emitting lasers (VCSELs) and the tools typically used to detect them and identify the cause. It describes the basic design and operation of VCSELs and explains that most failures are due to dislocations in the crystal structure of the materials from which the devices are made. Of the various methods used to analyze such defects, electroluminescence (EL) is by far the most powerful as demonstrated in several EL images included in the article. The article also discusses the use of EBIC analysis, FIB cross-sectioning, and thermally induced voltage alteration (TIVA).

This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.

Several technology-focused User's Groups met at ISTFA 2014 to discuss current issues and advances in their areas of interest. This article summarizes key discussion points from the Contactless Fault Isolation User's Group, the Nanoprobing User's Group, the Sample Prep/3-D Package User's Group, and the FIB User's Group.

This article summarizes major discussion points from four User’s Group meetings held at the ISTFA 2009 conference. The topics addressed are "Optical Techniques: Growth and Limitations," "Resolution of Nanoprobing for 45 nm and Beyond: New Challenges," "FIB," and "Fast ASIC Fault Isolation: Efficiency and Accurate Resolution of Software-Based Fault Isolation."

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

Advances in IC technology have made failure site localization extremely challenging. Through a series of case studies, the authors of this article show how such challenges can be overcome using EBIC/EBAC, current imaging, and nanoprobing. The cases involve a wide range of issues, including resistor chain defects, substrate leakage, microcracking, micro contamination, and open failures due to copper plating problems and missing vias.

STEM-EBIC imaging, a nano-characterization technique, has been used in the study of electrically active defects, minority carrier diffusion length, surface recombination velocity, and inhomogeneities in Si pn junctions. In this article, the authors explain how they developed and built a STEM-EBIC system, which they then used to determine the junction location of an InGaN quantum well LED. They also developed a novel FIB-based sample preparation method and a custom sample holder, facilitating the simultaneous collection of Z-contrast, EBIC, and energy dispersive spectroscopy images. The relative position of the pn junction with respect to the quantum well was found to be 19 ± 3 nm from the center of well.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

This article presents the results of a study conducted at Sandia National Labs to assess the effect of electrostatic discharge on surface micromachined MEMS devices. This failure mode has largely been overlooked because ESD failure mechanisms often mimic the effects of stiction-adhesion. To measure the susceptibility of MEMS devices to ESD, Sandia engineers built and tested a silicon microengine and a torsional ratcheting microactuator. Test results indicate that the effects of ESD are highly dependent on device design, component stiffness, and geometry and that slight modifications can bring improvements.

The 42nd International Symposium for Testing and Failure Analysis (ISTFA 2016) was held in Fort Worth, Texas, November 6-10, 2016. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.

The 43rd International Symposium for Testing and Failure Analysis (ISTFA 2017) was held in Pasadena, Calif., November 5-9, 2017. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.