Search Results for shallow trench isolation

Sandia National Laboratories manufactures 0.5 µm CMOS ICs using local oxidation of silicon (LOCOS) and shallow trench isolation (STI) technologies. A program based on burn-in and life tests is being used to qualify the process for military and space applications. Representative ICs from baseline wafer lots are assembled in ceramic packages and electrically tested before, during, and after burn-in and subsequent life tests. Two types of ICs are being used for this qualification, a 256K-bit SRAM and a microcontroller core. More than 600 ICs have passed qualification tests with very few failures, although recently, a group of SRAMs from a development wafer lot incorporating nonqualified processes had an usually high number of failures during their initial electrical test after packaging. This article describes the investigation that was conducted to determine the cause of these failures.

Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The work featured in this article takes advantage of chemically assisted focused ion beam processing with ultraviolet spectroscopy to destructively delayer integrated circuits starting from the shallow trench isolation layer, enabling high-resolution SEM imaging at each layer.

Weak open contacts are common in DRAM cell arrays where they act as a resistance between the cell capacitor and wordline transistor. This article discusses the role of weak open contacts in DRAM failures, the factors that influence their effect on read and write operations, and the complexities involved in assessing potential problems.

This article discusses the concept and intent of a construction analysis and the value it provides to manufacturers and users of integrated circuits. It describes the basic steps of a construction analysis for semiconductor devices and presents and interprets measurements and observations obtained from the analyses of several ICs.

Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.

Advances in IC technology have made failure site localization extremely challenging. Through a series of case studies, the authors of this article show how such challenges can be overcome using EBIC/EBAC, current imaging, and nanoprobing. The cases involve a wide range of issues, including resistor chain defects, substrate leakage, microcracking, micro contamination, and open failures due to copper plating problems and missing vias.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

Scanning probe microscopy (SPM) is widely used for fault isolation as well as diagnosing leakage current, detecting open circuits, and characterizing doping related defects. In this article, the author presents two SPM applications that are fairly uncommon but no less important in the scope of failure analysis. The first case involves the discovery of nano-steps on the surface of high-voltage NFETs, a phenomenon associated with stress-induced crystalline shift along the (111) silicon plane. In the second case, the author uses an AFM probe in the conductive mode to correlate tunneling current distribution with hot spots in high-k gate oxide films, which is shown to be a better indicator of oxide quality than rms surface roughness.

This article discusses the use of scanning-beam techniques such as EBIC, IBIC, and OBIC to optimize the design of edge-termination structures in vertical GaN and AlGaN power diodes.

Scanning capacitance microscopy (SCM) has proven to be an effective tool for investigating doping-related failure mechanism in ICs. The examples in this article show how the author used SCM to solve various problems including premature breakdown due to pattern misalignment, threshold voltage variations caused by poly gate doping anomalies, and source-drain leakage due to channeling effects.

Silicon pipeline defects are a growing concern in semiconductor manufacturing with no proposed methodology on how to effectively analyze them and separate the underlying causes. In light of this need, a study was conducted using complementary FA techniques to examine these unusual silicon crystal defects and gain a better understanding of their signature characteristics and their effect on device failure. This article, authored by the lead investigator, describes the tests that were performed and presents relevant findings and theories on the factors that contribute to "pipeline" and how they can be controlled. It also presents guidelines for distinguishing between pipeline and dislocation defects and explains how they are related.

This article provides an introduction to focused ion beam (FIB) circuit editing, covering the basic process along with best practices and procedures.

Recent developments in automated image acquisition and metrology using transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) have significantly improved the speed, precision, and usability of these techniques for controlling advanced semiconductor device manufacturing processes. As device dimensions have continued to shrink, these techniques may be needed to replace scanning electron microscopy (SEM) for the smallest critical dimension (CD) measurements. This article describes the use of automated S/TEM in a high-throughput CD-metrology workflow to support process development and control and explains how automated sample-preparation, data-acquisition, and metrology tools increase both throughput and data quality.

FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.

The 43rd International Symposium for Testing and Failure Analysis (ISTFA 2017) was held in Pasadena, Calif., November 5-9, 2017. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.

This article discusses the basic principles of dark current spectroscopy (DCS), a measurement technique that can detect and identify low levels of metal contaminants in CMOS image sensors. An example is given in which DCS is used to determine the concentration of tungsten and gold contaminants in an image sensor and estimate the dark current generated by a single atom of each metal.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

This article describes how focused ion beam (FIB) technology is being used in combination with various other analytical tools for failure and yield analysis of MEMS devices. It provides examples showing how FIB is used with TEM analysis, AFM analysis, scanning acoustic microscopy, and scanning laser microscopy.

Differential Hall effect metrology (DHEM) provides depth profiles of all critical electrical parameters through semiconductor layers at nanometer-level depth resolution. This article describes the relatively new method and shows how it is used to measure mobility and carrier concentration profiles in different materials and structures.