This column gives a broad picture of the technical issues facing the semiconductor industry and how they may affect microelectronics failure analysis. The three major trends addressed are (1) a shift to larger wafer sizes (450 mm); (2) the consolidation of manufacturing at the leading edge; and (3) strategies for dealing with the end of standard scaling (sometimes referred to as “More than Moore”).

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

Reflecting back on the past 45 years in semiconductor failure analysis, the columnist notes that the trend lines have deviated little over that time. He then goes on to point out the relatively few discontinuities, the latest of which, the emergence of the “invisible defect,” takes him back to the beginning of his journey.

The market for semiconductor manufacturing equipment has consolidated rapidly over the last decade; where there were once hundreds of potential customers, there are now perhaps a dozen in the first tier. This transformation has been driven primarily by the dramatic growth in the cost and complexity of the manufacturing process and has caused a shift in the priorities that guide purchasing decisions—from technical performance to asset utilization. These changes are also reflected in the failure analysis (FA) lab, where rising tool costs and operator expertise requirements have made it increasingly difficult to justify the investment required to maintain a complete state-of-the-art capability. Outsourcing some FA activity has become increasingly attractive.

Automation may be responsible for the loss of many jobs, but it has been and is likely to remain more of a help than a threat to semiconductor failure analysts.

This column reflects on the changes taking place in the semiconductor industry as it tries to live up to expectations for faster, better, cheaper ICs every two to three years in keeping with Moore's law.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

This column provides an update on the latest developments in 3D IC technology and outlines the work that still remains before the promises of full 3D integration can be realized.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

This column reflects on the effect mobile phones have had on process and packaging technology and failure analysis.

This month’s guest columnist shares his thoughts on the effects of consolidation and automation in the semiconductor industry and the importance of training for failure analysts.

This editorial discusses the emergence of chiplets and its potential impact on IC design, fabrication, and failure analysis.

Counterfeiting continues to be a concern in the electronics industry, particularly for microprocessors, memory chips, and high temperature range ICs. This article provides an understanding of the extent of the problem, identifies frequently copied parts, and proposes measures to help keep counterfeiters in check.

This column explains that silicon interposers, considered an interim solution to full 3D integration, may turn out to be more than a stepping stone along the path toward 3D ICs.

A recent trend in semiconductor failure analysis involves combining the use of different tools and techniques in order to acquire more accurate data at a faster rate. This article describes a new workflow that combines FIB, GIS, and nanoprobing, all performed at the same FIB tilt position. It also provides two examples in which the workflow is used.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.

With the growing complexity of new processes and the introduction of new materials, the need for product yield management and process control is placing unprecedented demands on failure analysis laboratories in the semiconductor industry. These demands are calling for faster and superior analytical capabilities to determine root-cause failure mechanisms in semiconductor devices fabricated using deep submicron processes. This article presents a new automated sample preparation technique that facilitates direct electrical contact to the area of interest, with a surface quality sufficient for scanning probe microscope analysis.

This article assesses the progress that has been made in the development and implementation of through-silicon via (TSV) technology, the work yet to be done, and the challenges associated with potential failure mechanisms.

The pace of development for 2.5-D packaging solutions appears to be accelerating as the timeline for the adoption of 3D through-silicon via (TSV) technology continues to slide. This column discusses the latest advancements in 2.5-D or interposer packaging technology and the growing number of applications.