This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.