Search Results for sample preparation

This article discusses the practice of FIB-based in situ lift-out, a sample preparation method that has proven particularly useful for failure analysis. It explains how samples are now being made for a wide range of TEM techniques, including holography, tomography, high-angle annular dark-field scanning, and electron energy-loss spectroscopy. In most cases, achieving optimal quality requires the use of alternate FIB milling angles, as in plan-view, sideways, and backside milling, all of which are discussed.

This paper describes a methodology for preparing contoured devices by using a milling machine in conjunction with a spectral reflectance measurement system for meeting ±5 μm remaining silicon thickness (RST) tolerances.

Failure analysts use a variety of machines for sample preparation, many of which are mechanical in nature. This article discusses the factors that determine the accuracy, resolution, and repeatability of XY positioning systems, rotary stages, and multiaxis machines. It identifies critical machine parameters and explains how environmental effects, runout, and geometric inaccuracies contribute to uncertainty and positioning error. It also assesses the precision, accuracy, and repeatability required for backside thinning and delayering systems.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Sample preparation is a critical step for dopant profiling of FinFET devices, especially when targeting individual fins. This article describes a sample-preparation technique based on low-energy, shallow-angle ion milling and shows how it minimizes surface amorphization and improves scanning capacitance microscopy (SCM) signals representative of local active dopant concentration.

This article describes an automated sample preparation process for SEM and TEM analysis based on submicron polishing. The method uses robotics, image processing, and a polishing wheel under computer control for a fully automated recipe-driven process that creates exact cross-sections with 0.1 μm accuracy.

The combination of microcleaving and precision broad ion beam techniques allows failure analysts to prepare site-specific specimens for SEM analysis with 0.5 μm accuracy. Microcleaving, as the article explains, uses the cleaving characteristics inherent in single-crystal semiconductor substrates. Because the substrate has significantly more mass than the process layers, it dictates the overall cross-section quality and precision of the sample. The cleave loses no material, preserves the integrity of the designated area, and enables analysis of both sides of the cross-section. When the cleave is off-set due to a buried target or when debris lies on the surface of the cross-section, ion beam etching and coating are used to fine tune the cleave location and remove debris prior to SEM analysis.

With the growing complexity of new processes and the introduction of new materials, the need for product yield management and process control is placing unprecedented demands on failure analysis laboratories in the semiconductor industry. These demands are calling for faster and superior analytical capabilities to determine root-cause failure mechanisms in semiconductor devices fabricated using deep submicron processes. This article presents a new automated sample preparation technique that facilitates direct electrical contact to the area of interest, with a surface quality sufficient for scanning probe microscope analysis.

A new and improved sample preparation technique was developed by Wang. This technique uses an FIB instrument for the 90° rotation of a small portion of the specimen on the original grid by taking advantage of static force. All sample preparation steps, including thin-section creation and sample tilting, can be accomplished in a single process. The procedure is monitored in a high-resolution FIB instrument to assure a 100% success rate. Figure 1 shows a scanning electron microscope image of a 3D TEM sample with two rotated sections. The original TEM sample is a lift-out sample laid on carbon film.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

This article describes a sample preparation technique by which specific areas on integrated circuits can be manually polished to TEM transparency. The technique, called tripod polishing or the wedge method, produces cross-section samples within a few hours that require little or no additional thinning for TEM analysis. The method can also be used to prepare plan view TEM samples as well as samples for SEM analysis and light microscopy.

The scribe-and-cleave method is a widely used sample preparation technique, although numerous challenges make it less than ideal. A new indent-and-cleave approach described in this article provides improved results, even on samples previously considered uncleavable. Several case studies are presented to demonstrate the capabilities of the new technique.

An optically polished silicon surface with controlled sample thickness is the key to successful backside imaging. Achieving that manually can be very difficult in cases where ICs are encapsulated in packaging materials. This article describes the challenges involved with traditional (manual) backside silicon sample preparation techniques and the improvements obtainable with automation.

Shortcuts in failure analysis are sometimes to save time or money or because equipment or expertise is unavailable. This article presents simple but effective solutions in four areas, including deprocessing, FIB milling, microcleaving, and TEM sample preparation, that may help analysts work through or around such situations.

The Electronic Device Failure Analysis Society established the Die-Level Post-Isolation Domain Council to provide an overview of the upcoming challenges in this area and guide technique developments for next-generation analytical tools. This column summarizes the findings of the council in the areas of sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. It is a preview of the full roadmap document, which is in preparation to be released to the EDFAS community.

Recent developments in automated image acquisition and metrology using transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) have significantly improved the speed, precision, and usability of these techniques for controlling advanced semiconductor device manufacturing processes. As device dimensions have continued to shrink, these techniques may be needed to replace scanning electron microscopy (SEM) for the smallest critical dimension (CD) measurements. This article describes the use of automated S/TEM in a high-throughput CD-metrology workflow to support process development and control and explains how automated sample-preparation, data-acquisition, and metrology tools increase both throughput and data quality.

STEM-EBIC imaging, a nano-characterization technique, has been used in the study of electrically active defects, minority carrier diffusion length, surface recombination velocity, and inhomogeneities in Si pn junctions. In this article, the authors explain how they developed and built a STEM-EBIC system, which they then used to determine the junction location of an InGaN quantum well LED. They also developed a novel FIB-based sample preparation method and a custom sample holder, facilitating the simultaneous collection of Z-contrast, EBIC, and energy dispersive spectroscopy images. The relative position of the pn junction with respect to the quantum well was found to be 19 ± 3 nm from the center of well.

This article provides a summary of the presentations given at the four User’s Group meetings at ISTFA 2012. Each user group focused on one of the following topics: nanoprobing, contactless fault isolation, focused ion beam, and sample preparation.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

This article presents a failure analysis workflow tailored for complex ICs and device packages. The FA flow determines the root cause of failures using nondestructive analysis and advanced sample preparation techniques. The nondestructive tests typically used are X-ray radiography, scanning acoustic microscopy, time domain reflectometry, and magnetic current imaging. To gain access to interconnect failures, laser ablation is used, typically in combination with chemical etching to finish the decapsulation process. Repackaging is also part of the FA flow and is briefly discussed.