Integrated circuits embedded in everyday devices face an increased risk of tampering and intrusion. In this article, the authors explain how reverse engineering techniques, including automated image analysis, can be employed to provide trust and assurance when dealing with commercial off-the-shelf chips.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

This column suggests that developing 3D structural models as tools for observing and exploring failures in the virtual domain could prove instrumental in avoiding failure without committing hardware. Likewise, instead of building hardware to systematically evaluate failures in the presence of random effects, virtualization through a 3D model could provide a completely user-defined environment for conducting controlled experiments. In such a virtual environment, systematic and random behaviors can be introduced and parsed to provide greater clarity in the search for root causes of failure.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

This article discusses the concept and intent of a construction analysis and the value it provides to manufacturers and users of integrated circuits. It describes the basic steps of a construction analysis for semiconductor devices and presents and interprets measurements and observations obtained from the analyses of several ICs.

This article proposes a design for a real-time Trojan detection system and explores possible solutions to the challenge of large-scale SEM image acquisition. One such solution, a deep-learning approach that generates synthetic micrographs from layout images, shows significant promise. Learning-based approaches are also used to both synthesize and classify cells. The classification outcome is matched with the design exchange format file entry to ensure the purity of the underlying IC.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

Scanning microwave impedance microscopy (sMIM) is an electrical measurement technique that can be used to determine dopant profiles in semiconductor devices. This article describes the basic setup and implementation of the method and demonstrates its use in the cross-sectional analysis of NMOS power transistors.

Plasma focused ion beam (PFIB) systems can generate ion beams with much higher current and are therefore able to remove larger volumes of material at much faster rates while still maintaining precise control of the beam and its milling action. This article explains how the improved performance of PFIB is leading to new applications in delayering, deprocessing, and site-specific failure analysis.

This column reflects on the effect mobile phones have had on process and packaging technology and failure analysis.

Liquid metal ion and plasma beam FIB systems are widely used in the semiconductor industry for TEM lamella preparation, circuit edit, and cross-sectional analysis. This article compares the deprocessing capability of a Ga FIB with that of a Xe plasma FIB. Both systems were used to delayer an Intel 14 nm processor from M8 down to the transistor contacts. As the images in the article show, a 100 × 100 µm window was opened by the Xe plasma FIB and a 20 × 20 µm window was opened with the Ga FIB. Related issues such as processing time, end point detection, and surface roughness are also discussed.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

Several technology-focused User's Groups met at ISTFA 2014 to discuss current issues and advances in their areas of interest. This article summarizes key discussion points from the Contactless Fault Isolation User's Group, the Nanoprobing User's Group, the Sample Prep/3-D Package User's Group, and the FIB User's Group.

At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

Voltage contrast followed by electron beam induced current imaging is an effective approach for isolating IC failures. This article briefly reviews the physics of signal generation for both techniques and presents several examples illustrating how this powerful combination contributes to advanced defect localization.

Time domain reflectometry (TDR) is widely used to measure the electrical length of conductors. It has also proven useful for isolating failures in ICs. This article describes a variation of the method, called comparative TDR, that overcomes inherent timing limitations and simplifies use. It discusses the basic hardware requirements of the new technique and presents examples demonstrating its use on opens and shorts in ceramic flip-chip packages.